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公开(公告)号：US20240172450A1
公开(公告)日：2024-05-23
申请号：US18421986
申请日：2024-01-25
发明人： Weiliang Jing , Kailiang Huang , Junxiao Feng , Zhengbo Wang
CPC分类号： H10B53/30 , H01L29/40111 , H01L29/42392 , H10B53/10 , H10B53/20 , H10B53/40
摘要： A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.
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公开(公告)号：US11923272B2
公开(公告)日：2024-03-05
申请号：US17721919
申请日：2022-04-15
CPC分类号： H01L23/481 , H01L21/4814 , H10B12/0335 , H10B12/315 , H10B12/50 , H10B53/10 , H10B53/30 , H10B53/40
摘要： Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.
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公开(公告)号：US11888068B2
公开(公告)日：2024-01-30
申请号：US17502546
申请日：2021-10-15
发明人： Antonino Rigano , Marcello Mariani
IPC分类号： H01L29/786 , H01L29/66 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , G11C11/22 , G11C11/408 , H01L21/28 , H10B12/00 , H10B51/30 , H10B51/40 , H10B53/30 , H10B53/40
CPC分类号： H01L29/78642 , G11C11/2257 , G11C11/4085 , H01L27/124 , H01L27/127 , H01L27/1222 , H01L27/1255 , H01L29/40111 , H01L29/42392 , H01L29/4908 , H01L29/516 , H01L29/6684 , H01L29/66742 , H01L29/78391 , H01L29/78618 , H01L29/78651 , H10B12/0335 , H10B12/315 , H10B12/50 , H10B51/30 , H10B51/40 , H10B53/30 , H10B53/40
摘要： Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US11877438B2
公开(公告)日：2024-01-16
申请号：US18076888
申请日：2022-12-07
发明人： Antonino Rigano
CPC分类号： H10B12/34 , G11C11/221 , H01L29/7827 , H10B12/0383 , H10B53/30 , H10B53/40
摘要： A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.
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公开(公告)号：US11770936B1
公开(公告)日：2023-09-26
申请号：US17517349
申请日：2021-11-02
IPC分类号： G11C16/04 , H10B53/30 , G11C11/24 , H10B53/40 , G11C11/404 , G11C11/405
CPC分类号： H10B53/30 , G11C11/24 , H10B53/40 , G11C11/404 , G11C11/405
摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
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公开(公告)号：US11729995B1
公开(公告)日：2023-08-15
申请号：US17516572
申请日：2021-11-01
IPC分类号： G11C11/00 , H10B53/30 , G11C11/24 , H10B53/40 , G11C11/404 , G11C11/405
CPC分类号： H10B53/30 , G11C11/24 , H10B53/40 , G11C11/404 , G11C11/405
摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
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公开(公告)号：US11688447B2
公开(公告)日：2023-06-27
申请号：US17685833
申请日：2022-03-03
发明人： Johannes Ocker
CPC分类号： G11C11/221 , G11C11/223 , G11C11/2273 , G11C11/2275 , H01L28/55 , H01L28/60 , H10B51/30 , H10B51/40 , H10B53/30 , H10B53/40
摘要： According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.
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公开(公告)号：US20230113576A1
公开(公告)日：2023-04-13
申请号：US18053966
申请日：2022-11-09
发明人： Makoto Kitagawa
IPC分类号： H10B53/30 , H10B53/40 , G11C11/22 , H01L29/786
摘要： Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.
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公开(公告)号：US12108607B1
公开(公告)日：2024-10-01
申请号：US17502942
申请日：2021-10-15
发明人： Noriyuki Sato , Debraj Guhabiswas , Tanay Gosavi , Niloy Mukherjee , Amrita Mathuriya , Sasikanth Manipatruni
摘要： An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
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公开(公告)号：US20240276736A1
公开(公告)日：2024-08-15
申请号：US18589134
申请日：2024-02-27
摘要： Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.
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