公开(公告)号：US4175286A

公开(公告)日：1979-11-20

申请号：US870697

申请日：1978-01-19

Applicant: Arthur C. Hunter ,  Lloyd E. Norman

Inventor： Arthur C. Hunter ,  Lloyd E. Norman

IPC: B41J29/393 ,  G06F3/12 ,  G06F11/06

CPC classification number: B41J29/393

Abstract: An electronic apparatus having a keyboard and an output device, such as a thermal printer unit. The apparatus, including its printer unit, is burn-in tested by an electronic system built into the apparatus. The system includes a memory, a circuit for storing a preselected or predetermined alphanumeric code in the memory and a circuit for repetitively causing the printer unit to print the contents of the memory. A delay system may be incorporated which causes the apparatus to enter a wait mode between printing operations. The period of time that the system is in the wait mode may be either a fixed duration or of a selected duration. In the embodiment disclosed, the apparatus is an electronic calculator.

Abstract translation: 具有键盘和输出装置的电子设备，例如热敏打印机单元。 该设备，包括其打印机单元，由内置于设备中的电子系统进行老化测试。 该系统包括存储器，用于在存储器中存储预选或预定的字母数字代码的电路，以及用于重复地使打印机单元打印存储器的内容的电路。 可以并入延迟系统，其使设备进入打印操作之间的等待模式。 系统处于等待模式的时间段可以是固定持续时间或选定持续时间。 在所公开的实施例中，该装置是电子计算器。

公开(公告)号：US4084232A

公开(公告)日：1978-04-11

申请号：US771606

申请日：1977-02-24

Applicant: John M. Woods ,  Bruce C. Keene

Inventor： John M. Woods ,  Bruce C. Keene

IPC: G06F11/00 ,  G05F1/577 ,  G06F1/28 ,  H02H1/00 ,  G06F11/06 ,  G05B13/02 ,  G08B29/00 ,  H02H7/00

CPC classification number: H02H1/0069 ,  G05F1/577 ,  G06F1/28 ,  Y10T307/461 ,  Y10T307/707

Abstract: A data processing system includes as part of its power circuits, a number of converter circuits, each coupled to a different one of the power supply units which are to provide different voltages for distribution and use throughout the system. Each of the power supply circuits furnish a 24 volt dc power confidence signal to a central ac power input entry panel which applies the power confidence signals to the converter circuits. Each converter circuit includes an optically coupled isolator circuit which converts the 24 volt dc signal to a noise free low voltage logic level suitable for utilization by the low level high speed logic circuits included within the system. The output noise free low voltages provided by the converter circuits are in turn applied to a corresponding number of confidence input lines of a system interface unit which includes a plurality of ports, each port connected to a different module within the data processing system. The states of the low voltage logical level signals are stored in a status register. When the operating system determines that a unit is inoperative due to a power supply unit failure, it can logically disconnect the port having a module having the failure. Additionally, one of the converter circuits provides a second output signal which is used to enable the clock circuits during system power up only after the system has been placed in a known state.

公开(公告)号：US4051461A

公开(公告)日：1977-09-27

申请号：US680851

申请日：1976-04-27

Applicant: Masahiro Hashimoto ,  Kenichi Furumaya

Inventor： Masahiro Hashimoto ,  Kenichi Furumaya

IPC: G06F12/12 ,  G06F9/22 ,  G06F12/08 ,  G06F12/16 ,  G11C29/00 ,  G06F11/06 ,  G06F11/10 ,  G06F13/00

CPC classification number: G11C29/70 ,  G06F12/0864

Abstract: In a memory hierarchy system comprising a main memory for storing data and a buffer memory for holding a part of the data stored in the main memory as a copy of the main memory data, the data on the buffer memory is frequently replaced by the data on the main memory so as to hold in the buffer memory the data which is very frequently used. The buffer memory also holds the data which is in an area of the main memory where an irremediable fault occurred and that data is prevented from being replaced. Therefore, the buffer memory is substituted for the fault area of the main memory so that a fail soft system is attained.

公开(公告)号：US3905023A

公开(公告)日：1975-09-09

申请号：US38855173

申请日：1973-08-15

Applicant: BURROUGHS CORP

Inventor： PERPIGLIA FRANK JOSEPH

IPC: G06F11/16 ,  G06F1/26 ,  G06F11/07 ,  G06F11/20 ,  G06F11/22 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F11/06

CPC classification number: G06F11/2038 ,  G06F1/26 ,  G06F11/073 ,  G06F11/0748 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1666 ,  G06F11/201 ,  G06F11/2015 ,  G06F11/22 ,  G06F12/1491

Abstract: A multiprogrammed multiprocessing information processing system having independently operating computing, input/output, and memory modules through an exchange, and interacting with a multilevel operating system designed to automatically makes optimum use of all system resources by controlling system resources and by scheduling jobs in the multiprogramming mix of the processing system. In operation, the operating system insures that all system resources are automatically allocated to meet the needs of the programs introduced into the system as well as insuring the continuous and automatic reassignment of resources, the initiation of new jobs, and the monitoring of their performance. System reliability is achieved by the incorporation of error detection circuit throughout the system, by single-bit correction of errors in memory, by recording errors for software analysis and by modularization and redundacy of critical elements.

Abstract translation: 一种多程序多处理信息处理系统，其通过交换机具有独立运行的计算，输入/输出和存储器模块，并与多级操作系统进行交互，该多级操作系统被设计为通过控制系统资源并通过调度作业来自动地最佳地利用所有系统资源 处理系统的多程序组合。 在运行中，操作系统确保所有系统资源被自动分配以满足引入到系统中的程序的需求，并确保资源的持续和自动重新分配，启动新的工作以及对其性能的监控。 通过在整个系统中并入误差检测电路，通过对存储器中的错误进行单位校正，通过记录软件分析的错误以及关键元件的模块化和冗余来实现系统可靠性。

公开(公告)号：US3833890A

公开(公告)日：1974-09-03

申请号：US34118373

申请日：1973-03-14

Applicant: INT STANDARD ELECTRIC CORP

Inventor： TOURNIER C ,  BUZY DEBAT J

IPC: G06F11/20 ,  G06F13/40 ,  H04Q3/545 ,  G06F11/06 ,  G05B9/02

CPC classification number: H04Q3/54558 ,  G06F11/20 ,  G06F13/4022

Abstract: A safety arrangement that avoids double access from paired duplicated circuits to commonly controlled equipment. The safety arrangement includes two safety circuits each associated with one of the duplicated circuits. Each of the safety circuits comprising a seizure bistable circuit whose output is connected to a priority arrangement. The output of the priority arrangement is connected to an operation bistable circuit. The priority arrangement is driven by one of two synchronized oscillators one in each safety circuit associated with duplicated circuit, the two oscillators operating in phase opposition.

Abstract translation: 一种避免从配对复制电路到普通受控设备双重访问的安全设置。 安全装置包括两个安全电路，每个安全电路与一个复制电路相关联。 每个安全电路包括一个咬合双稳态电路，其输出端与优先级排列相连。 优先级布置的输出连接到操作双稳态电路。 优先级排列由两个同步振荡器中的一个驱动，每个同步振荡器在与复制电路相关联的每个安全电路中有一个，两个振荡器以相位相反的方式工作。

公开(公告)号：US3812468A

公开(公告)日：1974-05-21

申请号：US25287472

申请日：1972-05-12

Applicant: BURROUGHS CORP

Inventor： WOLLUM J ,  BIRCHMEIER H ,  SHARP R

IPC: G06F11/00 ,  G06F15/177 ,  G06F11/06 ,  G06F15/00

CPC classification number: G06F11/2035 ,  G06F11/2023 ,  G06F15/177

Abstract: This disclosure relates to a multiprocessing system having a plurality of different units such as processor, I/O units and so forth that can be arranged into individual processing groups, the functions of which units can be redesignated in order to maintain continuous operation of the system should a malfunction occur in any one or more of such units. Each processing group is provided with a redesignator unit to represent that group, which redesignator unit senses malfunctions in any of the units in the corresponding group or in other groups and controls the reconfiguration or redesignation cycle. The system further includes a reconfiguration control unit that includes a designation memory in which are stored different designation parameters for the functional designation of the different like units in the system. These various sets of redesignation or reconfiguration control signals are selected from the designation memory in response to condition sensed in the system by the various redesignator units.

公开(公告)号：US08102690B2

公开(公告)日：2012-01-24

申请号：US12577704

申请日：2009-10-12

Applicant: Richard Michael Parent ,  Ryan Andrew Jurasek ,  Dave Eugene Chapmen

Inventor： Richard Michael Parent ,  Ryan Andrew Jurasek ,  Dave Eugene Chapmen

IPC: G11C5/00 ,  G11C8/00 ,  G06F11/06

CPC classification number: G11C7/1018 ,  G11C5/025 ,  G11C7/1045 ,  G11C2207/105

Abstract: A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.

Abstract translation: 在特定操作模式下降低功耗的芯片系统包括：DDR3芯片，包括：设置在DDR3芯片中心的多个焊盘; 和一组银行，每个银行都有一个特定的逻辑地址，围绕着这些垫。 芯片系统还包括：耦合到DDR3芯片的时钟，用于控制数据传输速率; 以及存储器控制器，其耦合到时钟，用于根据特定操作模式来协调与相关过程的传输数据，并且用于选择性地重新分配存储体逻辑地址。

公开(公告)号：US07369493B2

公开(公告)日：2008-05-06

申请号：US10754043

申请日：2004-01-08

Applicant: James A. Ibezim ,  Stephanie Parlamas ,  Amy J. Rupert ,  Harish Samarasinghe

Inventor： James A. Ibezim ,  Stephanie Parlamas ,  Amy J. Rupert ,  Harish Samarasinghe

IPC: G01R31/08 ,  G06F11/06 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

CPC classification number: H04L47/122 ,  H04L29/06027 ,  H04L47/10 ,  H04L65/1006 ,  H04L65/80 ,  H04L69/40 ,  H04Q3/0091

Abstract: Upon detection of an overload condition at a network element, the network element sends two messages to those other network elements which may potentially send request messages to the overloaded network element. If the network utilizes the SIP signaling protocol, then the messages sent by an overloaded network element are SIP INVITE and SIP CANCEL. The CANCEL message comprises an indication that the sending network element is unavailable and an amount of time which the recipient network elements are to wait before sending any requests to the overloaded network node. Upon receipt of these messages, the receiving network elements wait for a delay time period before sending any additional request messages to the overloaded network element. During the waiting period, the waiting network elements may send request messages to network elements other than the overloaded network element which provide functionality similar to that of the overloaded network element.

Abstract translation: 在网络元件检测到过载状况时，网络元件将两个消息发送到可能向重载的网络元件发送请求消息的那些其他网络元件。 如果网络使用SIP信令协议，则由网络过载发送的消息是SIP INVITE和SIP CANCEL。 CANCEL消息包括发送网络元件不可用的指示和接收方网络元件在向重载的网络节点发送任何请求之前要等待的时间量。 在接收到这些消息之后，接收网络元件在发送任何附加请求消息到超载网元之前等待延迟时间段。 在等待期间，等待的网络元件可以向网络元件发送请求消息，而非网络元件提供与过载的网络元件类似的功能。

公开(公告)号：US5754568A

公开(公告)日：1998-05-19

申请号：US795230

申请日：1997-02-10

Applicant: Jan Braasch

Inventor： Jan Braasch

IPC: G01B11/00 ,  G01B21/00 ,  G01D5/244 ,  G01D5/249 ,  G06F11/06

CPC classification number: G01D5/24461 ,  G01D5/24466 ,  G01D5/2495

Abstract: A position measuring system for increasing operational dependability, wherein the absolute position is generated by scanning a chain code and erroneously scanned code words are detected and excluded from further processing. A plurality of codes are scanned at areas of the code track which are distanced from each other and are supplied to an error check device.

Abstract translation: 一种用于增加操作可靠性的位置测量系统，其中通过扫描链码产生绝对位置，并且检测并排除进一步处理的错误扫描的代码字。 在代码轨道的彼此远离的区域处扫描多个代码并将其提供给错误检查装置。

公开(公告)号：US4418384A

公开(公告)日：1983-11-29

申请号：US194655

申请日：1980-10-06

Applicant: Thomas O. Holtey ,  Richard P. Kelly ,  Steven S. Noyes ,  James C. Raymond

Inventor： Thomas O. Holtey ,  Richard P. Kelly ,  Steven S. Noyes ,  James C. Raymond

IPC: H04M11/06 ,  G06F13/00 ,  G06F13/42 ,  H04L1/00 ,  H04L1/22 ,  H04L29/02 ,  H04M11/00 ,  G06F3/00 ,  G06F11/06

CPC classification number: H04L1/0083 ,  G06F13/4226

Abstract: A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.

Abstract translation: 以位定向协议（BOP）操作模式操作的数据处理系统感测发送欠载; 也就是说，子系统没有从微处理器接收到足够快的数据，以保持通过通信线路的同步传输。 装置感测发射欠载状态，并产生包含8到13个连续二进制1位的位的中止序列。