公开(公告)号：US4084232A

公开(公告)日：1978-04-11

申请号：US771606

申请日：1977-02-24

Applicant: John M. Woods ,  Bruce C. Keene

Inventor： John M. Woods ,  Bruce C. Keene

IPC: G06F11/00 ,  G05F1/577 ,  G06F1/28 ,  H02H1/00 ,  G06F11/06 ,  G05B13/02 ,  G08B29/00 ,  H02H7/00

CPC classification number: H02H1/0069 ,  G05F1/577 ,  G06F1/28 ,  Y10T307/461 ,  Y10T307/707

Abstract: A data processing system includes as part of its power circuits, a number of converter circuits, each coupled to a different one of the power supply units which are to provide different voltages for distribution and use throughout the system. Each of the power supply circuits furnish a 24 volt dc power confidence signal to a central ac power input entry panel which applies the power confidence signals to the converter circuits. Each converter circuit includes an optically coupled isolator circuit which converts the 24 volt dc signal to a noise free low voltage logic level suitable for utilization by the low level high speed logic circuits included within the system. The output noise free low voltages provided by the converter circuits are in turn applied to a corresponding number of confidence input lines of a system interface unit which includes a plurality of ports, each port connected to a different module within the data processing system. The states of the low voltage logical level signals are stored in a status register. When the operating system determines that a unit is inoperative due to a power supply unit failure, it can logically disconnect the port having a module having the failure. Additionally, one of the converter circuits provides a second output signal which is used to enable the clock circuits during system power up only after the system has been placed in a known state.

公开(公告)号：US4091455A

公开(公告)日：1978-05-23

申请号：US752345

申请日：1976-12-20

Applicant: John M. Woods ,  Marion G. Porter ,  Earnest M. Monahan

Inventor： John M. Woods ,  Marion G. Porter ,  Earnest M. Monahan

IPC: G06F13/12 ,  G06F11/07 ,  G06F11/22 ,  G06F11/273 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  G06F11/00

CPC classification number: G06F11/0772 ,  G06F11/0745 ,  G06F11/2294

Abstract: An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the logical pair preventing the disconnected processing unit from communicating with other modules. The control logic circuits further include circuits which in response to special commands from a good processor are operative to condition via a special line, circuits in the disconnected processing unit to apply status signals representative of the contents of a control register to the system interface unit. The other circuits within the system interface unit in response to a further command condition certain switching circuit networks for loading the status signals into one of the registers included in the system interface unit for subsequent analysis by system routines.

Abstract translation: 输入/输出处理系统包括多个模块，其包括连接以作为逻辑对操作的至少一对处理单元和具有多个端口的系统接口单元。 每个端口连接到不同的模块之一，用于互连模块对，用于通过包括在系统接口单元中的多个交换电路网络进行通信。 系统接口单元还包括用于断开逻辑对的每个处理器的控制逻辑电路，防止断开的处理单元与其他模块通信。 控制逻辑电路还包括电路，其响应于来自良好处理器的特殊命令可操作以经由特殊线路进行调节，断开处理单元中的电路将代表控制寄存器的内容的状态信号应用于系统接口单元。 系统接口单元内的其他电路响应于另外的命令条件，某些转换电路网络将状态信号加载到系统接口单元中包括的寄存器之一中，以便随后由系统程序进行分析。

公开(公告)号：US4099234A

公开(公告)日：1978-07-04

申请号：US741632

申请日：1976-11-15

Applicant: John M. Woods ,  Marion G. Porter ,  Donald V. Mills ,  Edward F. Weller, III ,  Garvin Wesley Patterson ,  Earnest M. Monahan

Inventor： John M. Woods ,  Marion G. Porter ,  Donald V. Mills ,  Edward F. Weller, III ,  Garvin Wesley Patterson ,  Earnest M. Monahan

IPC: G06F11/18 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/00 ,  G06F15/16 ,  G06F11/00

CPC classification number: G06F11/1641 ,  G06F11/0745 ,  G06F11/079 ,  G06F11/165 ,  G06F11/2089 ,  G06F11/22

Abstract: An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwithstanding the fact that the first processing unit tests well. Following reconfiguration, the operating system associated with the system provides periodic testing of the good processing unit, thereby ensuring that the system continues to operate reliably.

Abstract translation: 输入/输出系统至少包括一对处理单元和系统接口装置，用于在主处理单元或主处理单元的控制下在正常系统操作期间比较两对的两半所产生的结果。 系统接口装置包括比较电路，用于检测每一半的结果与序列控制逻辑电路之间的错误比较，序列控制逻辑电路在发生误比较时进行解锁或解除配置，以预定的方式建立 处理单元有故障。 系统接口设备在处理单元内具有一定的最小置信度的信号指示，继续使用存储的诊断例程对处理器进行测试，以确定处理单元中的哪一个是良好的。 然后停止坏处理单元的操作，并使良好处理单元能够继续系统运行。 为了确保可靠的处理，尽管第一个处理单元测试良好，但是当误差比较不能与与该对中的一个相关联的错误状况不相关时，该对的两个部分被测试。 在重新配置之后，与系统相关联的操作系统提供良好处理单元的周期性测试，从而确保系统继续可靠地运行。

公开(公告)号：US4070704A

公开(公告)日：1978-01-24

申请号：US686975

申请日：1976-05-17

Applicant: Jaime Calle ,  Robert J. Garvey ,  Earnest M. Monahan ,  George L. Parris ,  Jerome J. Twibell ,  John M. Woods

Inventor： Jaime Calle ,  Robert J. Garvey ,  Earnest M. Monahan ,  George L. Parris ,  Jerome J. Twibell ,  John M. Woods

IPC: G06F11/20 ,  G06F15/177 ,  G06F11/00 ,  G06F13/00

CPC classification number: G06F15/177 ,  G06F11/20

Abstract: An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

Abstract translation: 自动重新配置硬件功能，用于在输入/输出处理器引导加载的启动阶段发生故障时自动更改本地内存/处理器配置并重新启动引导加载顺序。 当引导加载请求源自系统控制台或中央系统时，自动重新配置逻辑被启用。 一旦引导启动请求，就可以尝试所有可能的本地存储器/输入输出处理器（IOPP）配置，而无需进一步的手动干预。 如果没有配置成功，I0P配置面板上将显示引导加载错误指示。