公开(公告)号：US20040263369A1

公开(公告)日：2004-12-30

申请号：US10669280

申请日：2003-09-23

Inventor： Andreas Wiesbauer ,  Martin Clara ,  Thomas Potscher ,  Hubert Weinberger ,  Jorg Hauptmann ,  Thomas Magesacher

IPC: H03M001/20

CPC classification number: H03M1/66 ,  H03M1/201 ,  H03M3/33 ,  H03M3/458 ,  H03M3/50

Abstract: The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog converters. In this arrangement, a digital/analog conversion is performed which, in particular, is suitable for VDSL systems. A transmitted digital transmission signal (110) is supplied to a mixing unit (201) and in the mixing unit (201), a receive noise signal (211) applied to a receive noise source terminal (209) is superimposed on the digital transmission signal (110). An interpolation filter unit (203), in combination with a subsequent noise shaping device (205), provides an increase in the frequency bandwidth, resulting in suitable oversampling.

公开(公告)号：US5825318A

公开(公告)日：1998-10-20

申请号：US769823

申请日：1996-12-19

Applicant: Ara Patapoutian ,  Kevin D. Fisher ,  Bruce D. Buch

Inventor： Ara Patapoutian ,  Kevin D. Fisher ,  Bruce D. Buch

IPC: G11B5/55 ,  G11B5/596 ,  G11B20/10 ,  G11B20/12 ,  G11B21/08 ,  G11B21/10 ,  H03M1/20 ,  H03M1/48

CPC classification number: G11B5/59605 ,  G11B20/10009 ,  G11B21/085 ,  G11B21/106 ,  G11B5/5547 ,  G11B5/59655 ,  H03M1/201 ,  G11B20/1258

Abstract: An analog-to-digital converter circuit in a sampling data detection channel of a disk drive synchronously samples user data in the data track areas at a first quantization resolution and samples servo bursts from the spoke areas at a second quantization resolution effectively greater than said first quantization resolution. An offset circuit provides a predetermined analog offset signal to a combining circuit which combines it with an incoming analog signal to provide a composite signal during a spoke servo burst sampling interval. An analog-to-digital converter samples the composite signal during the servo spoke burst sampling interval, and synchronously samples the analog signal during a user data sampling interval. A digital averaging circuit averages the servo spoke samples over a predetermined averaging interval to provide averaged burst samples having increased bit resolution.

Abstract translation: 磁盘驱动器的采样数据检测通道中的模拟 - 数字转换器电路以第一量化分辨率同步采样数据轨道区域中的用户数据，并且以比第二量化分辨率有效地大的第二量化分辨率从轮辐区域采样伺服脉冲串 量化分辨率。 偏移电路向组合电路提供预定的模拟偏移信号，该组合电路将其与输入模拟信号组合，以在辐射伺服脉冲串采样间隔期间提供复合信号。 模数转换器在伺服轮询突发采样间隔期间对复合信号进行采样，并在用户数据采样间隔期间同步采样模拟信号。 数字平均电路在预定的平均间隔上对伺服轮辐样本进行平均，以提供具有增加的比特分辨率的平均突发样本。

公开(公告)号：US5451947A

公开(公告)日：1995-09-19

申请号：US200613

申请日：1994-02-23

Applicant: Gary Morrison

Inventor： Gary Morrison

IPC: H03M1/48 ,  G01R19/25 ,  G01R21/133 ,  H03M1/20

CPC classification number: G01R19/25 ,  G01R21/133 ,  H03M1/201

Abstract: A system for analogue to digital conversion comprising a means (4) for receiving an input analogue signal, a dither generator for adding a dither signal and an analogue to digital converter (2) for converting the combined input signal and dither signal to a digital value, characterized in that the dither generator provides a dither signal of a form comprising a first periodic dither signal having superimposed and being shaped by a second signal having at least one component which varies the first periodic dither signal over at least one quantization interval of the analogue to digital converter.

Abstract translation: 一种用于模数转换的系统，包括用于接收输入模拟信号的装置（4），用于添加抖动信号的抖动发生器和用于将组合输入信号和抖动信号转换成数字值的模数转换器（2） 其特征在于，所述抖动发生器提供包括第一周期性抖动信号的抖动信号，所述第一周期性抖动信号已被叠加并被第二信号整形，所述第二信号具有至少一个分量，所述至少一个分量通过所述模拟信号的至少一个量化间隔改变第一周期性抖动信号 到数字转换器。

公开(公告)号：US4963881A

公开(公告)日：1990-10-16

申请号：US425146

申请日：1989-10-23

Applicant: Michael R. Franceschini

Inventor： Michael R. Franceschini

IPC: H03M1/20

CPC classification number: H03M1/201

Abstract: A method and apparatus for enhancing the resolution of an analog-to-digital converter. The method uses the addition of a second analog waveform to a first analog signal which is to be converted. When the composite signal is converted to digital form, this enhances the effective resolution of the A/D converter with respect to the first signal. Integration of the composite digital signal causes the effects of the second waveform to average to zero. The result is an enhanced resolution signal without undesired effects of the added second signal.

Abstract translation: 一种用于增强模数转换器的分辨率的方法和装置。 该方法使用向要转换的第一模拟信号添加第二模拟波形。 当复合信号被转换为数字形式时，这增强了A / D转换器相对于第一信号的有效分辨率。 复合数字信号的积分使第二波形的效果平均为零。 结果是增强的分辨率信号，没有不必要的添加的第二信号的影响。

公开(公告)号：US4644324A

公开(公告)日：1987-02-17

申请号：US810974

申请日：1985-12-19

Applicant: Tetsuro Araki ,  Hiroyuki Onda

Inventor： Tetsuro Araki ,  Hiroyuki Onda

IPC: H03M1/20 ,  H03M1/00 ,  H03M1/04 ,  H03M1/66

CPC classification number: H03M1/201

Abstract: A system for converting an audio or like data signal from digital to analog form, with the addition of dither (white noise) to the digital input, with or without the subsequent removal of the dither from the analog output, for the reduction of quantization noise. Included is a network of n adders, equal in number to the n bits of the coded data signal, for adding in bit parallel form the digital data signal and the digital dither signal. Generated by an analog dither generator, the dither signal is transformed by an analog to digital converter into an m bit coded digital output, m being less than n, prior to delivery to the adder network. Some, preferably all, of the m bits of the digital dither signal are each added to, for example, two different ones of the n bits of the digital data signal so that, for instance, an eight bits analog to digital converter can be used for the provision of a digital dither signal to be added to a 16 bits digital audio signal. The adder network is connected to a digital to analog converter for converting the bit parallel addition of the data and dither signals into analog form.

Abstract translation: 一种用于将音频或类似数据信号从数字形式转换成模拟形式的系统，在数字输入端添加抖动（白噪声），伴随或不用随后从模拟输出中去除抖动，以减少量化噪声 。 包括与编码数据信号的n位数相等的n个加法器的网络，用于以数字数据信号和数字抖动信号的位并行形式相加。 由模拟抖动发生器产生的抖动信号由模拟数字转换器转换成m位编码的数字输出，m小于n，然后传送到加法器网络。 数字抖动信号的m位中的一些，优选地，全部每一个都被添加到例如数字数据信号的n位中的两个不同的位，使得例如可以使用8位模数转换器 用于提供要添加到16位数字音频信号的数字抖动信号。 加法器网络连接到数模转换器，用于将数据和抖动信号的位并行加法转换为模拟形式。

公开(公告)号：US20240137040A1

公开(公告)日：2024-04-25

申请号：US18490931

申请日：2023-10-19

Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Arindam SANYAL

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/20

CPC classification number: H03M1/462 ,  H03M1/0668 ,  H03M1/201

Abstract: A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.

公开(公告)号：US11652494B1

公开(公告)日：2023-05-16

申请号：US17555226

申请日：2021-12-17

Applicant: Lawrence Livermore National Security, LLC ,  Tektronix, Inc.

Inventor： Brandon Walter Buckley ,  Ryan Douglas Muir ,  Daniel G. Knierim

IPC: H03M1/20 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03M1/124

Abstract: Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a discrete set of analog dither offset voltages, wherein at least two of the discrete set of analog dither offset voltages are different from each other, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein the waveform has a waveform duration, generate a timing alignment to align each waveform of the analog repetitive signal and the corresponding analog dither offset voltage over the waveform duration, combining, based on the timing alignment, each waveform and the corresponding analog dither offset voltage over the waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal.

公开(公告)号：US20170250701A1

公开(公告)日：2017-08-31

申请号：US15441868

申请日：2017-02-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akane HIROSHIMA ,  Yuji SHIMIZU ,  Yutaka ONO

IPC: H03M1/48 ,  H02K11/225

CPC classification number: H03M1/485 ,  G01B7/30 ,  G01D5/2053 ,  H02K11/225 ,  H02P6/16 ,  H03M1/201

Abstract: The present invention provides a signal processor that improves a resolution of a phase detection without increasing a clock frequency of a controller or decreasing a frequency of an excitation signal. A signal processor 10 includes a comparator 11 that compares a signal obtained by phase modulating a carrier frequency at a rotor rotation angle of a resolver with a dither signal.

公开(公告)号：US20160352347A1

公开(公告)日：2016-12-01

申请号：US15153711

申请日：2016-05-12

Applicant: ANALOG DEVICES, INC.

Inventor： PAUL R. FERNANDO ,  SUDARSHAN ANANDA NATARAJAN

IPC: H03M1/10 ,  H03M1/20 ,  H04N5/378 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/0639 ,  H03M1/1061 ,  H03M1/201 ,  H03M1/466 ,  H03M1/468

Abstract: Disclosed herein are systems for calibrating an analog-to-digital converter (ADC) device, as well as related devices and methods. In some embodiments, a system for calibrating an ADC device may include an ADC device, wherein the ADC device includes an ADC and a dither source, and wherein the ADC device is to apply a set of calibration parameters to generate digital outputs. The system may also include calibration circuitry, coupled to the ADC device, to determine which of multiple sets of values of calibration parameters results in the digital outputs having the lowest amount of noise, and to cause the ADC device to apply the calibration parameters associated with the lowest noise.

Abstract translation: 本文公开了用于校准模数转换器（ADC）装置以及相关装置和方法的系统。 在一些实施例中，用于校准ADC器件的系统可以包括ADC器件，其中ADC器件包括ADC和抖动源，并且其中ADC器件将应用一组校准参数以产生数字输出。 该系统还可以包括耦合到ADC器件的校准电路，以确定校准参数的多组值中的哪一组导致具有最低噪声量的数字输出，并且使得ADC器件施加与 噪音最低

公开(公告)号：US09461665B1

公开(公告)日：2016-10-04

申请号：US14837049

申请日：2015-08-27

Applicant: Korea University Research and Business Foundation

Inventor： Chulwoo Kim ,  Sejin Park

IPC: H03M1/46 ,  H03M1/06

CPC classification number: H03M1/462 ,  H03M1/0607 ,  H03M1/201 ,  H03M1/468

Abstract: A Successive Approximated Register Analog-to-Digital Converter (“SARADC”) is provided that includes: a bootstrapping unit that receives and samples analog signals; and an Analog-to-Digital Conversion Unit (“ADCU”) that converts the analog signals into digital signals and outputs the digital signals. ADCU has a resolution increasing in response to an intentionally injected offset voltage. In this case, ADCU includes Capacitor Arrays (“CAs”) having: a differential structure each including reference voltage application capacitors having different capacitances and an Offset Voltage Injection Capacitor (“OVIC”); a delay cell that operates CAs in an asynchronous mode; Reference Transfer Switch Units (“RTSUs”) that apply a reference voltage to CAs; a comparator that compares output voltages of CAs; and Successive Approximated Register Logics (“SARLs”). SARLs control operations of RTSUs in response to an output signal of the comparator and perform control so that a reference voltage is applied to OVICs when the output of the comparator is abnormal.

Abstract translation: 提供了一种连续近似寄存器模数转换器（“SARADC”），其包括：自举单元，其接收和采样模拟信号; 以及将模拟信号转换为数字信号并输出​​数字信号的模数转换单元（“ADCU”）。 ADCU响应于有意注入的失调电压而具有增加的分辨率。 在这种情况下，ADCU包括具有：差分结构的电容阵列（“CA”），每个差分结构包括具有不同电容的参考电压施加电容器和偏移电压注入电容器（“OVIC”）; 以异步模式操作CA的延迟单元; 参考转换开关单元（“RTSU”），将参考电压应用于CA; 比较器，用于比较CA的输出电压; 和连续近似寄存器逻辑（“SARL”）。 SARL根据比较器的输出信号控制RTSU的操作，并执行控制，以便当比较器的输出异常时，将参考电压施加到OVIC。