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    Receiver for RF signals
    15.
    发明授权
    Receiver for RF signals 失效
    RF信号接收器

    公开(公告)号：US06298226B1

    公开(公告)日：2001-10-02

    申请号：US09203001

    申请日：1998-11-30

    Applicant: Stephen L. Lloyd ,  Pete Good

    Inventor： Stephen L. Lloyd ,  Pete Good

    IPC: H04B110

    CPC classification number: H03F3/456 ,  H03F1/303 ,  H03F3/45511 ,  H03F3/4556 ,  H03F2200/294 ,  H03F2200/372

    Abstract: A communications device includes a direct-conversion receiver for a radio frequency (RF) signal which is configured to receive the RF signal during defined time slots. A first input receives the RF signal and a first output outputs a baseband signal derived from the RF signal. A mixer module is configured to receive the RF signal and a local signal which is generated by a local oscillator. The mixer module generates an output signal which includes the baseband signal and an offset component. An amplifier module is connected between the first output and the mixer module, and includes a feedback loop which has in a backward path, a track-and-hold circuit. The track-and-hold circuit is configured to track the offset component during a first time slot and to hold a value of the offset component at an end of the first time slot until a subsequent second time slot begins. This held value is applied during the second time slot to the output signal in order to provide for fast compensation of the offset component.

    Abstract translation: 通信设备包括用于射频（RF）信号的直接转换接收器，其被配置为在限定的时隙期间接收RF信号。 第一输入接收RF信号，第一输出输出从RF信号导出的基带信号。 混频器模块被配置为接收由本地振荡器产生的RF信号和本地信号。 混频器模块产生包括基带信号和偏移分量的输出信号。 放大器模块连接在第一输出和混频器模块之间，并且包括反向通路中具有跟踪和保持电路的反馈回路。 跟踪和保持电路被配置为在第一时隙期间跟踪偏移分量，并且在第一时隙的结束处保持偏移分量的值直到随后的第二时隙开始。 在第二时隙期间将该保持值应用于输出信号，以便提供偏移分量的快速补偿。

    Bias rail buffer circuit and method
    16.
    发明授权
    Bias rail buffer circuit and method 有权
    偏置轨道缓冲电路及方法

    公开(公告)号：US06297699B1

    公开(公告)日：2001-10-02

    申请号：US09692017

    申请日：2000-10-19

    Applicant: Kenneth W. Murray ,  Joel M. Halbert

    Inventor： Kenneth W. Murray ,  Joel M. Halbert

    IPC: H03F326

    CPC classification number: H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

    Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

    Abstract translation: 根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。 用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。 用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号 。 偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰 。

    Wide-band linearization technique
    17.
    发明授权
    Wide-band linearization technique 有权

    公开(公告)号：US06218902B1

    公开(公告)日：2001-04-17

    申请号：US09294315

    申请日：1999-04-20

    Applicant: William Kung

    Inventor： William Kung

    IPC: H03F345

    CPC classification number: H03F3/4556 ,  H03F2203/45454

    Abstract: A conventional differential transistor pair is provided with a dynamic bias circuit. The input voltage signal for the differential pair is also full-wave rectified and the rectified signal is used to bias dynamically the differential pair while the input voltage signal is being applied. One or more bias transistors having a control electrode fed with the rectified signal is connected in series with the differential pair. The result is that as the input signal magnitude increases the amount of bias increases dynamically and increases linearly for larger signals. Desired responses other than linearity can be achieved by making the signal that is fed to the rectifier vary according to any predetermined function.

    Wideband operational amplifier
    18.
    发明授权
    Wideband operational amplifier 有权
    宽带运算放大器

    公开(公告)号：US6163216A

    公开(公告)日：2000-12-19

    申请号：US215402

    申请日：1998-12-18

    Applicant: Kenneth W. Murray ,  Joel M. Halbert

    Inventor： Kenneth W. Murray ,  Joel M. Halbert

    IPC: H03F3/30 ,  H03F3/343 ,  H03F3/45

    CPC classification number: H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

    Abstract: A wideband operational amplifier in accordance with the present invention overcomes many shortcomings of the prior art. A wideband operational amplifier may be configured to provide a high output voltage and high output current. The amplifier may comprise an input stage having a first input buffer and a second input buffer, and an output stage amplifier having an output buffer. The input stage may also include current mirrors configured to facilitate a lower input offset voltage and lower input voltage noise. Moreover, the operational amplifier may also provide a wide common-mode input range and full power bandwidth simultaneously.

    Abstract translation: 根据本发明的宽带运算放大器克服了现有技术的许多缺点。 宽带运算放大器可以被配置为提供高输出电压和高输出电流。 放大器可以包括具有第一输入缓冲器和第二输入缓冲器的输入级，以及具有输出缓冲器的输出级放大器。 输入级还可以包括配置成便于较低输入偏移电压和较低输入电压噪声的电流镜。 此外，运算放大器还可以同时提供宽的共模输入范围和全功率带宽。

    Differential gain stage for use in a standard bipolar ECL process
    19.
    发明授权
    Differential gain stage for use in a standard bipolar ECL process 失效
    差分增益级用于标准双极ECL工艺

    公开(公告)号：US5420524A

    公开(公告)日：1995-05-30

    申请号：US157242

    申请日：1993-11-26

    Applicant: Stephen Webster

    Inventor： Stephen Webster

    IPC: H01L27/06 ,  H01L21/8222 ,  H03F1/08 ,  H03F3/45 ,  H03K19/0175 ,  H03K19/086 ,  H03K19/003

    CPC classification number: H03F3/4556 ,  H03F1/083 ,  H03F3/45098 ,  H03F2203/45416 ,  H03F2203/45458 ,  H03F2203/45702

    Abstract: An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor. The third and fourth capacitor structures are located at a second spaced relationship from the substrate. The third capacitor is connected to the first capacitor and the connection forms a first node. The fourth capacitor is connected to the second capacitor and the connection forms a second node. The differential gain stage also includes first and second buffers. The first buffer has an input connected to the non-inverting input of the gain stage and an output connected to the first node. The second buffer has an input connected to the inverting input of the gain stage and an output connected to the second node.

    Abstract translation: 用于双极单片集成电路的改进的差分增益级。 集成电路由半导体衬底形成，差分增益级包括第一和第二双极晶体管。 第一晶体管的基极和第二晶体管的基极分别形成用于增益级的差分输入，包括非反相和反相输入。 晶体管的集电极形成差分输出。 差分增益级包括电容器级，包括：峰值电容器，以及第一，第二，第三和第四电容器结构。 峰值电容器耦合在第一和第二晶体管的发射极之间。 第一和第二电容器结构位于与衬底之间的第一间隔关系处，并且第一电容器耦合到第一晶体管的发射极，而第二电容耦合到第二晶体管的发射极。 第三和第四电容器结构位于与衬底之间的第二间隔关系。 第三电容器连接到第一电容器，并且连接形成第一节点。 第四电容器连接到第二电容器，并且连接形成第二节点。 差分增益级还包括第一和第二缓冲器。 第一缓冲器具有连接到增益级的同相输入的输入端和连接到第一节点的输出。 第二缓冲器具有连接到增益级的反相输入的输入端和连接到第二节点的输出。

    Operational amplifier circuit
    20.
    发明授权
    Operational amplifier circuit 失效
    运算放大器电路

    公开(公告)号：US4463319A

    公开(公告)日：1984-07-31

    申请号：US404580

    申请日：1982-08-02

    Applicant: Mark B. Kearney

    Inventor： Mark B. Kearney

    IPC: H03F3/30 ,  H03F3/45

    CPC classification number: H03F3/4521 ,  H03F3/3067 ,  H03F3/45121 ,  H03F3/4556 ,  H03F2203/45028 ,  H03F2203/45232 ,  H03F2203/45366

    Abstract: An operational amplifier includes a PNP differential amplifier operable for low common mode input voltages and an NPN differential amplifier operable for high common mode input voltages so that the operational amplifier is operable over a range of common mode input voltages that includes substantially the positive and negative supply voltages.

    Abstract translation: 运算放大器包括可用于低共模输入电压的PNP差分放大器和可操作用于高共模输入电压的NPN差分放大器，使得运算放大器可在大体上包括正和负电源的共模输入电压范围内工作 电压。

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