公开(公告)号：US06429744B2

公开(公告)日：2002-08-06

申请号：US09904806

申请日：2001-07-13

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F326

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

摘要翻译： 根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。 用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。 用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号 。 偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰 。

公开(公告)号：US06552613B2

公开(公告)日：2003-04-22

申请号：US10209767

申请日：2002-07-31

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F345

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for providing a high output voltage and current reference signal suitably includes an output buffer configured with a compensation circuit for reducing disturbances introduced into the output stage amplifier circuit by voltage supply rails, such as parasitic ringing and other disturbances. The compensation circuit can suitably comprise a first compensation device, such as at least one capacitor, and a second compensation device, such as at least one capacitor. The compensation devices are suitably coupled between an input terminal of the output stage amplifier circuit and a pair of transistors proximate a pair of output transistors of the output stage amplifier circuit, and are configured to provide “pole-zero” compensation to the output stage amplifier circuit.

摘要翻译： 根据本发明的输出级放大器电路克服了现有技术的许多缺点。 用于提供高输出电压和电流参考信号的输出级放大器电路适当地包括配置有补偿电路的输出缓冲器，用于通过诸如寄生振铃和其他干扰的电压供应轨道减小引入到输出级放大器电路中的干扰。 补偿电路可以适当地包括诸如至少一个电容器的第一补偿装置和诸如至少一个电容器的第二补偿装置。 补偿装置适当地耦合在输出级放大器电路的输入端和靠近输出级放大器电路的一对输出晶体管的一对晶体管之间，并且被配置为向输出级放大器提供“极零”补偿 电路。

公开(公告)号：US06297699B1

公开(公告)日：2001-10-02

申请号：US09692017

申请日：2000-10-19

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F326

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

摘要翻译： 根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。 用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。 用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号 。 偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰 。

公开(公告)号：US6163216A

公开(公告)日：2000-12-19

申请号：US215402

申请日：1998-12-18

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F3/30 ,  H03F3/343 ,  H03F3/45

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A wideband operational amplifier in accordance with the present invention overcomes many shortcomings of the prior art. A wideband operational amplifier may be configured to provide a high output voltage and high output current. The amplifier may comprise an input stage having a first input buffer and a second input buffer, and an output stage amplifier having an output buffer. The input stage may also include current mirrors configured to facilitate a lower input offset voltage and lower input voltage noise. Moreover, the operational amplifier may also provide a wide common-mode input range and full power bandwidth simultaneously.

摘要翻译： 根据本发明的宽带运算放大器克服了现有技术的许多缺点。 宽带运算放大器可以被配置为提供高输出电压和高输出电流。 放大器可以包括具有第一输入缓冲器和第二输入缓冲器的输入级，以及具有输出缓冲器的输出级放大器。 输入级还可以包括配置成便于较低输入偏移电压和较低输入电压噪声的电流镜。 此外，运算放大器还可以同时提供宽的共模输入范围和全功率带宽。

公开(公告)号：US5623232A

公开(公告)日：1997-04-22

申请号：US534046

申请日：1995-09-26

申请人： Joel M. Halbert ,  Kenneth W. Murray ,  Dan Yuan

发明人： Joel M. Halbert ,  Kenneth W. Murray ,  Dan Yuan

IPC分类号： H01L27/02 ,  H03F3/30 ,  H03F1/30 ,  H03F3/213

CPC分类号： H01L27/0203 ,  H03F3/3076

摘要： A high speed integrated circuit operational amplifier chip first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. The most thermally sensitive transistors are disposed along or symmetrically about the thermal centerline to provide approximately balanced response by such transistors to differential heating by the output driver circuit. The bonding pads, which function as heat sinks, also are symmetrically disposed on or about the thermal centerline.

摘要翻译： 高速集成电路运算放大器芯片第一，第二，第三和第四连续边缘包括平行于第二和第四边缘的热中心线。 输出驱动器电路沿着第三边缘位于输出接合焊盘附近并且围绕热中心线大致对称地设置，以提供运算放大器芯片相对于热中心线的近似平衡的差分加热。 差分输入电路位于第一边缘附近并且围绕热中心线大致对称地设置，以将低增益差分输入电路中的匹配晶体管的近似平衡的响应提供给由差分加热产生的等温线。 最热敏感的晶体管围绕热中心线布置或对称地布置，以通过这种晶体管提供由输出驱动器电路的差分加热的近似平衡的响应。 用作散热器的接合焊盘也对称地设置在热中心线上或周围。

公开(公告)号：US06278326B1

公开(公告)日：2001-08-21

申请号：US09692370

申请日：2000-10-19

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F304

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.

摘要翻译： 根据本发明的电流镜电路克服了现有技术的许多缺点。 用于提供电流参考信号的电流镜电路适当地包括至少一个退化电阻器，以为较低电压噪声提供更多的退化，同时还包括至少一个钳位装置以防止电流镜的饱和。 钳位装置适当地包括至少一个二极管，例如肖特基型二极管。 此外，夹持装置可以适当地构造成有助于电流镜电路的更高的转换速率。

公开(公告)号：US5627495A

公开(公告)日：1997-05-06

申请号：US534039

申请日：1995-09-26

申请人： Joel M. Halbert ,  Kenneth W. Murray

发明人： Joel M. Halbert ,  Kenneth W. Murray

IPC分类号： H03F3/30 ,  H03F3/45 ,  H03F1/30

CPC分类号： H03F3/4521 ,  H03F3/3076 ,  H03F3/45094 ,  H03F2203/45028 ,  H03F2203/45366 ,  H03F2203/45371 ,  H03F2203/45392

摘要： A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. Low gain amplification circuit transistors are located adjacent to the low gain differential input circuit and disposed along the thermal centerline between the low gain differential input circuit and the output drive circuit stage to provide approximately balanced response to the low gain amplification circuit transistors to differential heating by the output driver circuit. Compensated bias current circuitry is located along the fourth edge and adjacent to the low gain amplification circuit transistors and the output driver circuit.

摘要翻译： 具有第一，第二，第三和第四连续边缘的高速集成电路运算放大器芯片包括平行于第二和第四边缘的热中心线。 输出驱动器电路沿着第三边缘位于输出接合焊盘附近并且围绕热中心线大致对称地设置，以提供运算放大器芯片相对于热中心线的近似平衡的差分加热。 低增益差分输入电路位于第一边缘附近并且围绕热中心线大致对称地设置，以将低增益差分输入电路中的匹配晶体管的大致平衡的响应提供给由差分加热产生的等温线。 低增益放大电路晶体管位于低增益差分输入电路附近，并沿着低增益差分输入电路和输出驱动电路级之间的热中心线设置，以向低增益放大电路晶体管提供近似平衡的响应，以通过 输出驱动电路。 补偿偏置电流电路沿着第四边缘并且邻近低增益放大电路晶体管和输出驱动器电路。

公开(公告)号：US4807147A

公开(公告)日：1989-02-21

申请号：US804224

申请日：1985-11-27

申请人： Joel M. Halbert ,  Myron J. Koen

发明人： Joel M. Halbert ,  Myron J. Koen

IPC分类号： G01R31/28 ,  H03M1/00 ,  G06F15/31 ,  G01R23/16

CPC分类号： G01R31/2834 ,  H03M1/1255

摘要： A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The sampling waveform digitizer system comprises a sampling comparator for comparing a sampled input signal with a first signal. An integrator coupled to the comparator provides an output signal from the integrator and becomes the first signal. An analog to digital converter provides the digital representation of the analog waveform. A controllable delay is provided for selecting a period of time for sampling the input signal by the comparator. A control device is provided for controlling the time the comparator samples the input signal. These combination of system features allow the digitizer to receive high speed analog waveforms and convert them to an accurate digital representation of the previously described high speed analog waveform.

摘要翻译： 提供了可扩展用于高速数据转换组件的动态测试的采样数字化仪系统。 采样波形数字转换器系统包括用于将采样的输入信号与第一信号进行比较的采样比较器。 耦合到比较器的积分器提供来自积分器的输出信号，并成为第一信号。 模数转换器提供模拟波形的数字表示。 提供了可控延迟，用于选择由比较器对输入信号进行采样的时间段。 提供控制装置用于控制比较器对输入信号进行采样的时间。 这些系统特性的组合使得数字化仪可以接收高速模拟波形，并将其转换成前述高速模拟波形的精确数字表示。

公开(公告)号：US4641246A

公开(公告)日：1987-02-03

申请号：US543853

申请日：1983-10-20

申请人： Joel M. Halbert ,  Myron J. Koen

发明人： Joel M. Halbert ,  Myron J. Koen

IPC分类号： G01R29/00 ,  G01R13/34 ,  G01R31/28 ,  H03M1/00 ,  H03M1/12 ,  G01R23/16 ,  G06F15/31

CPC分类号： H03M1/1071 ,  G01R31/2834 ,  H03M1/66

摘要： A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The system includes latching comparators which are supplied with the waveform under test and the comparator digital output is integrated by an operational amplifier integrator and fed back to the reference input of the latching comparator to form a comparator-integrator loop. A circuit provides strobe pulses which repeatedly sample the latch enable input of the comparators at a selected time/point until the integrator feedback forces the comparator reference input to be equal to the sample value of the input signal. At this point, an equilibrium state is reached where the integrator output oscillates about the sampled value, and when the loop settles, an analog-to-digital converter reads the final value under computer command. The sample point is computer controlled through a programmable delay line. A modified T-filter system operatively coupled between the output of the latching comparator and the input of the operational amplifier allows control of the integrator slope and filters out signal spikes to allow the required accuracy for high speed measurements while a similar modified T-filter is provided in the feedback loop for preventing disturbances at the integrator output which could be caused by the sampling of the latching comparators and for simultaneously preventing ringing and for rounding off signal spikes in the feedback loop. Various adaptions of the broad sampling digitizer system are provided for measuring the settling time of a 12-bit digital-to-analog converter whose common mode output reading is one-half LSB accuracy in under 40 nanoseconds and a dynamic tester for very fast-acting sample and hold amplifier circuits which measure, by independently controlling the polarity of the square wave or test stimulus signal and the polarity of the hold select command, such circuit parameters as acquisition time, sample-to-hold settling time, sample-to-hold offset, glitch amplitude, amplitude delay, hold mode feedthrough rejection, risetime, slew rate, and the like.

公开(公告)号：US06724260B2

公开(公告)日：2004-04-20

申请号：US10306212

申请日：2002-11-27

申请人： Alan Lee Varner ,  Ahmad Dashtestani ,  Joel M. Halbert ,  Michael A. Steffes

发明人： Alan Lee Varner ,  Ahmad Dashtestani ,  Joel M. Halbert ,  Michael A. Steffes

IPC分类号： H03F304

CPC分类号： H03F3/45112 ,  H03F3/45139 ,  H03F3/45174

摘要： A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.

摘要翻译： 提供具有较低输出阻抗输入级的低功率电流反馈放大器。 为了减小输出阻抗，输入级包括闭环输入缓冲器。 示例性输入缓冲器包括配置在总电流反馈放大器内的闭环电流反馈放大器，其中输入缓冲器的输出对应于整个电流反馈放大器的反相节点。 输入缓冲器的闭环配置通过使用从输入缓冲器的反相输入端耦合到输入缓冲器的输出的内部反馈电阻来实现，其对应于整个电流反馈放大器的反相输入端 。 闭环输入缓冲器实现了低输出阻抗，因为环路增益降低了输入缓冲器的输出阻抗。 具有较低的输出阻抗，即使在低电流实现下，电流反馈放大器的带宽变得更加独立于增益。