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公开(公告)号：US20030132828A1
公开(公告)日：2003-07-17
申请号：US10181306
申请日：2002-10-22
发明人： Masato Hashimoto , Yoshiro Morimoto , Akio Fukuoka , Hiroaki Kaito , Hiroyuki Saikawa , Toshiki Matsukawa , Junichi Hayase
IPC分类号： H01C007/00
CPC分类号： H01C17/006 , H01C1/14 , H01C1/148 , H01C7/001 , H01C17/075 , H01C17/283 , H01C17/288 , Y10T29/49082 , Y10T29/49083 , Y10T29/49098 , Y10T29/49099 , Y10T29/49101
摘要： An inexpensive fine resistor which do not require dimensional classifications of discrete substrates, eliminating a process of replacing a mask according to a dimensional ranking of each discrete substrate as in the prior art. The resistor includes discrete substrate (11) made into pieces by dividing an insulated substrate sheet along a first slit dividing portion and a second dividing portion perpendicular to the first dividing portion; top electrode layer (12) formed on a top face of discrete substrate (11); resistor layer (13) formed such that a part of resistor layer (13) overlaps top electrode layer (12); protective layers (14, 16) formed so as to cover resistor layer (13); side electrode layer (17) formed on a side face of discrete substrate (11) such that side electrode layer is electrically coupled to top electrode layer (12).
摘要翻译： 一种廉价的微型电阻器，其不需要离散衬底的尺寸分级，消除了像现有技术那样根据每个离散衬底的尺寸排列代替掩模的过程。 电阻器包括通过沿着第一狭缝分割部分分离绝缘基片并且垂直于第一分割部分的第二分割部分分成片的分立基片（11）。 形成在离散衬底（11）的顶面上的顶部电极层（12）; 电阻层（13）形成为使得电阻层（13）的一部分与顶部电极层（12）重叠; 形成为覆盖电阻层（13）的保护层（14,16）。 形成在分立衬底（11）的侧面上的侧面电极层（17），使得侧面电极层电耦合到顶部电极层（12）。
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公开(公告)号：US20030117258A1
公开(公告)日：2003-06-26
申请号：US10211271
申请日：2002-08-05
发明人： Young Min Kim , Young Chul Shin , Hae Youn Hwang
IPC分类号： H01C001/012
CPC分类号： H01C17/288 , H01C1/142
摘要： Disclosed is a thin film chip resistor having a structure suitable for effectively utilizing a slit substrate and simplifying a thin film forming step, in which thick film electrodes are formed on upper and lower surfaces of an insulator substrate, the thin film resistive layer is formed between thick film electrodes, and thin film electrodes connected to the thin film resistive layer are formed on both side portions of the upper surface of the insulator substrate. Furthermore, provided is a method for fabricating the thin film chip resistor, which can omit the step of forming thin film on a lower surface of the insulator substrate and minimize a defective proportion, which may occur during parting the insulator substrate along slits, by securing a space sufficient for contacting to probes with electrodes in a laser trimming step.
摘要翻译： 公开了一种薄膜片式电阻器，其具有适于有效利用狭缝基板的结构，并简化薄膜形成步骤，其中在绝缘体基板的上表面和下表面上形成厚膜电极，薄膜电阻层形成在 连接到薄膜电阻层的薄膜电极和薄膜电极形成在绝缘体基板的上表面的两侧部分上。 此外，提供了一种制造薄膜片式电阻器的方法，其可以省略在绝缘体基板的下表面上形成薄膜的步骤，并且通过确保在绝缘体基板沿狭缝分开时可能发生的缺陷比例最小化 在激光修整步骤中足以与电极接触的空间。
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公开(公告)号：US20020036564A1
公开(公告)日：2002-03-28
申请号：US09974272
申请日：2001-10-09
发明人： Noboru Furukawa , Masahiko Kawase , Yasunori Ito
IPC分类号： H01C007/10
CPC分类号： H01C7/008 , H01C17/288 , Y10T29/49082 , Y10T29/49083
摘要： Thermistor chips are produced by preparing ceramic green sheets, applying an inorganic material such as a glass paste on these green sheets in areas including lines along which they are to be later cut, stacking a plurality of these green sheets one on top of another to obtain a stacked body, obtaining chips by cutting this stacked body along those pre-specified lines and subjecting these chips to a firing process to obtain sintered bodies, and forming outer electrodes on mutually opposite end surfaces of these sintered bodies. A thermistor chip thus produced has a thermistor element having outer electrodes on its mutually opposite end surfaces, and diffused layers of an inorganic material having a higher specific resistance than material of the thermistor element. These diffused layers are formed proximally to externally exposed surfaces of the thermistor element.
摘要翻译： 热敏电阻芯片是通过制备陶瓷生片，将这些生片上的无机材料如玻璃糊在其以后被切割的线上的区域中进行加工而制成的，将多个这些生片叠加在一起，从而获得 层叠体，通过沿着这些预定线切割该层叠体而获得芯片，并对这些芯片进行烧成工序以获得烧结体，并在这些烧结体的相对的两个端面上形成外部电极。 如此制造的热敏电阻芯片具有在其相对的端面上具有外电极的热敏电阻元件和比热敏电阻元件的材料具有更高电阻率的无机材料的扩散层。 这些扩散层在热敏电阻元件的外露表面的近侧形成。
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公开(公告)号：US3794517A
公开(公告)日：1974-02-26
申请号：US3794517D
申请日：1971-12-28
申请人： PHILIPS CORP
发明人： YPERMAN J , BELHOMME C
CPC分类号： C04B35/4682 , C23C14/18 , H01B1/02 , H01B1/08 , H01C1/1406 , H01C7/045 , H01C17/288 , Y10S428/929 , Y10T428/12528 , Y10T428/12611
摘要： A METHOD IS SHOWN FOR INCREASING THE STABILITY OF THE ELECTRICAL RESISTANCE OF N-TYPE SEMICONDUCTOR BODIES PROVIDED WITH OHMIC CONTACT ELECTRODES. THE METHOD COMPRISES FIRST VACUUM DEPOSITING CHROMIUM ON THE SEMICONDUCTOR BODY AND THEN VACUUM DEPOSITING A SOLDERABLE METAL ON THE CHROMIUM LAYER. THIS ABSTRACT IS IN NO WAY INTENDED TO BE A DESCRIPTION OF THE INVENTION DEFINED BY THE CLAIMS.
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15.发明授权Ohmic contact electrode to semiconducting ceramics and a method for making the same 失效OHMIC接触电极到半导体陶瓷及其制造方法
公开(公告)号：US3586534A
公开(公告)日：1971-06-22
申请号：US3586534D
申请日：1969-04-28
发明人： NITTA TSUNEHARU , KUITO AKIO , NAGASE KANEOMI , IGUCHI TAKASHI , TAKI HIROMITSU
CPC分类号： H01C17/288
摘要： METHOD FOR PROVIDING OHMIC CONTACT TO AN OXIDE SEMICONDUCTING CERAMIC BY IMMERSING THE CERAMIC IN AN AQUEOUS SOLUTION OF NICKEL CHLORIDE, HYPOPHOSPHITE AND SODIUM CITRATE TO DEPOSIT AN ALLOY OF NICKEL AND PHOSPHORUS ON THE CERAMIC BODY BY AUTOCATALYTIC REACTION, THE AQUEOUS SOLUTION BEING MAINTAINED THROUGHOUT THE PERIOD OF IMMERSION AT A TEMPERATURE OF 90-100*C. AND PH OF 3-10.
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公开(公告)号：US3039952A
公开(公告)日：1962-06-19
申请号：US80182159
申请日：1959-03-25
申请人： WESTERN ELECTRIC CO
IPC分类号： H01C17/28
CPC分类号： H01C17/288
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公开(公告)号：US20170104054A1
公开(公告)日：2017-04-13
申请号：US15386256
申请日：2016-12-21
IPC分类号： H01L49/02 , H01L21/762 , H01L23/522 , H01L23/528 , H01L23/62 , H01C17/12 , H01L27/02 , H01L29/06 , H01C7/10 , H01C7/112 , H01C17/00 , H01C7/12 , H01L21/02 , H01L23/64
CPC分类号： H01C7/108 , H01C7/006 , H01C7/1013 , H01C7/112 , H01C7/12 , H01C17/006 , H01C17/06553 , H01C17/12 , H01C17/245 , H01C17/288 , H01L21/02175 , H01L21/022 , H01L21/02266 , H01L21/762 , H01L23/5226 , H01L23/528 , H01L23/62 , H01L23/647 , H01L27/0248 , H01L28/20 , H01L28/24 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.
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公开(公告)号：US09536732B2
公开(公告)日：2017-01-03
申请号：US14885512
申请日：2015-10-16
CPC分类号： H01C7/108 , H01C7/006 , H01C7/1013 , H01C7/112 , H01C7/12 , H01C17/006 , H01C17/06553 , H01C17/12 , H01C17/245 , H01C17/288 , H01L21/02175 , H01L21/022 , H01L21/02266 , H01L21/762 , H01L23/5226 , H01L23/528 , H01L23/62 , H01L23/647 , H01L27/0248 , H01L28/20 , H01L28/24 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.
摘要翻译： 一种使用低温溅射技术制造横向配置的薄膜压敏电阻浪涌保护装置的结构和方法，其不会损坏与正在制造的压敏电阻相邻的IC器件部件。 横向薄膜压敏电阻可以由在第二金属氧化物层和第二金属氧化物层之间的交替区域的连续层组成，所述第二金属氧化物层和第二金属氧化物层之间形成在两个横向隔开的电极之间，使用低温溅射工艺，随后进行低温退
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公开(公告)号：US20160254144A1
公开(公告)日：2016-09-01
申请号：US14885512
申请日：2015-10-16
CPC分类号： H01C7/108 , H01C7/006 , H01C7/1013 , H01C7/112 , H01C7/12 , H01C17/006 , H01C17/06553 , H01C17/12 , H01C17/245 , H01C17/288 , H01L21/02175 , H01L21/022 , H01L21/02266 , H01L21/762 , H01L23/5226 , H01L23/528 , H01L23/62 , H01L23/647 , H01L27/0248 , H01L28/20 , H01L28/24 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.
摘要翻译： 一种使用低温溅射技术制造横向配置的薄膜压敏电阻浪涌保护装置的结构和方法，其不会损坏与正在制造的压敏电阻相邻的IC器件部件。 横向薄膜压敏电阻可以由在第二金属氧化物层和第二金属氧化物层之间的交替区域的连续层组成，所述第二金属氧化物层和第二金属氧化物层之间形成在两个横向隔开的电极之间，使用低温溅射工艺，随后进行低温退火工艺
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公开(公告)号：US20080211619A1
公开(公告)日：2008-09-04
申请号：US12030281
申请日：2008-02-13
申请人： Michael Belman , Leonid Akhtman
发明人： Michael Belman , Leonid Akhtman
IPC分类号： H01C1/012
CPC分类号： H01C1/034 , H01C17/288
摘要： A chip resistor includes an insulating substrate 11, top terminal electrodes 12 formed on top surface of the substrate using silver-based cermet, bottom electrodes 13, resistive element 14 that is situated between the top terminal electrodes 12 and overlaps them partially, an optional internal protective coating 15 that covers resistive element 14 completely or partially, an external protective coating 16 that covers completely the internal protection coating 15 and partially covers top terminal electrodes 12, a plated layer of nickel 17 that covers face sides of the substrate, top 12 and bottom 13 electrodes, and overlaps partially external protective coating 16, finishing plated layer 18 that covers nickel layer 17. The overlap of nickel layer 17 and external protective layer 16 possesses a sealing property because of metallization of the edges of external protective layer 16 prior to the nickel plating process.
摘要翻译： 芯片电阻器包括绝缘基板11，使用银基金属陶瓷在基板的顶表面上形成的顶部端子电极12，底部电极13，位于顶部端子电极12之间并与其部分重叠的电阻元件14，可选内部 完全或部分覆盖电阻元件14的保护涂层15，完全覆盖内部保护涂层15并且部分地覆盖顶部端子电极12的外部保护涂层16，覆盖基底的正面的镍17的镀层，顶部12和 底部13个电极，并且重叠部分外部保护涂层16，覆盖镍层17的整理镀层18。 镍层17和外部保护层16的重叠由于在镀镍过程之前的外部保护层16的边缘的金属化而具有密封性。
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