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    Redirecting guest-generated events to an event aggregator in a networked virtualization environment
    11.
    发明授权
    Redirecting guest-generated events to an event aggregator in a networked virtualization environment 有权
    将客户机生成的事件重定向到联网虚拟化环境中的事件聚合器

    公开(公告)号：US09135051B2

    公开(公告)日：2015-09-15

    申请号：US13667094

    申请日：2012-11-02

    Applicant: Red Hat Israel, Ltd.

    Inventor： Gilad Chaplik ,  Haim Ateya

    IPC: G06F9/455 ,  H04L12/24 ,  G06F9/54 ,  G06F11/00

    CPC classification number: G06F9/45558 ,  G06F9/54 ,  G06F11/00 ,  G06F2009/45595 ,  G06F2201/00 ,  H04L41/0213

    Abstract: A method for integrating responses to asynchronous events is provided. A hypervisor of a host receives a request from a network manager to re-direct asynchronous events from a guest to an address of an event aggregation manager distinct from an address of the network manager. The hypervisor receives an asynchronous event having a destination address of the network manager from the guest. The hypervisor maps the destination address of the network manager to the address of the event aggregation manager. The hypervisor transmits the asynchronous event to the event aggregation manager.

    Abstract translation: 提供了一种用于将响应集成到异步事件的方法。 主机的管理程序接收来自网络管理器的请求，以将来自客户机的异步事件重新定向到与网络管理器的地址不同的事件聚合管理器的地址。 管理程序从guest虚拟机接收到具有网络管理器的目的地址的异步事件。 管理程序将网络管理器的目标地址映射到事件聚合管理器的地址。 虚拟机管理程序将异步事件发送到事件聚合管理器。

    Integrated circuit and method of operation
    12.
    发明授权
    Integrated circuit and method of operation 失效
    集成电路和操作方法

    公开(公告)号：US5642487A

    公开(公告)日：1997-06-24

    申请号：US292481

    申请日：1994-08-18

    Applicant: David Walter Flynn ,  Philip Brian Endecott

    Inventor： David Walter Flynn ,  Philip Brian Endecott

    IPC: G06F13/38 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3193 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/42 ,  G06F13/00

    CPC classification number: G06F1/10 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/31725 ,  G06F1/08 ,  G01R31/31937 ,  G06F2201/00

    Abstract: An integrated circuit includes a plurality of data handling devices and a data buffer for enabling transfer of data between the internal data handling devices and one or more external data handling devices external to the integrated circuit. A controller responds to an original clock signal for supplying a clock signal to control data transfer between the data handling devices. The controller includes a delay circuit operable to delay the original clock signal to generate a delayed clock signal, and includes a selector for inhibiting operation of the delay circuit and for selecting the original clock signal for controlling data transfer from an internal data handling device to another data handling device. The selector also enables operation of the delay circuit and selects the delayed clock signal for controlling data transfer from an external data handling device to an internal data handling device.

    Abstract translation: 集成电路包括多个数据处理装置和数据缓冲器，用于在内部数据处理装置与集成电路外部的一个或多个外部数据处理装置之间传送数据。 控制器响应原始时钟信号以提供时钟信号以控制数据处理装置之间的数据传送。 控制器包括延迟电路，可延迟原始时钟信号以产生延迟的时钟信号，并且包括用于禁止延迟电路的操作和选择用于控制从内部数据处理装置到另一个的数据传送的原始时钟信号的选择器 数据处理装置。 选择器还使能延迟电路的操作，并选择延迟的时钟信号以控制从外部数据处理装置到内部数据处理装置的数据传送。

    Position-measuring device and method for operating the same
    15.
    发明授权
    Position-measuring device and method for operating the same 有权
    位置测量装置及其操作方法

    公开(公告)号：US09303972B2

    公开(公告)日：2016-04-05

    申请号：US14028566

    申请日：2013-09-17

    Applicant: DR. JOHANNES HEIDENHAIN GmbH

    Inventor： Johann Oberhauser ,  Bernhard Schmied ,  Jannik Jens Rosenlehner-Emde ,  Werner Schwaiger ,  Thomas Schweizer ,  Hubert Mayer ,  Marc Oliver Tiemann

    IPC: G01B7/30 ,  G01D5/244 ,  G01D5/245 ,  G06F1/00

    CPC classification number: G01B7/30 ,  G01D5/24438 ,  G01D5/24476 ,  G01D5/2455 ,  G06F1/00 ,  G06F2101/00 ,  G06F2201/00

    Abstract: A position-measuring device includes a code carrier having a first graduation track and a second graduation track, the second graduation track being an incremental graduation track. A first detector system is configured to scan the graduation tracks so as to generate first position signals. A second detector system is configured to scan the second graduation track so as to generate second position signals. A first position-processing unit is configured to process the first position signals so as to yield a first absolute position value. A second position-processing unit is configured to process the second position signals so as to yield a second absolute position value. The first position-processing unit is configured to feed an absolute auxiliary position value to the second position-processing unit. The second position-processing unit is initializable with the absolute auxiliary position value.

    Abstract translation: 位置测量装置包括具有第一刻度轨道和第二刻度轨道的代码载体，所述第二刻度轨道是增量刻度轨道。 第一检测器系统被配置为扫描分度轨迹以便产生第一位置信号。 第二检测器系统被配置为扫描第二刻度轨道以便产生第二位置信号。 第一位置处理单元被配置为处理第一位置信号以产生第一绝对位置值。 第二位置处理单元被配置为处理第二位置信号以产生第二绝对位置值。 第一位置处理单元被配置为将绝对辅助位置值馈送到第二位置处理单元。 第二位置处理单元可以用绝对辅助位置值初始化。

    TAMPER RESISTANT ELECTRONIC SYSTEM UTILIZING ACCEPTABLE TAMPER THRESHOLD COUNT
    18.
    发明申请
    TAMPER RESISTANT ELECTRONIC SYSTEM UTILIZING ACCEPTABLE TAMPER THRESHOLD COUNT 有权
    耐冲击电子系统使用可接受的夯锤计数

    公开(公告)号：US20130187706A1

    公开(公告)日：2013-07-25

    申请号：US13354657

    申请日：2012-01-20

    Applicant: Travis R. Hebig ,  Joseph Kuczynski ,  Robert E. Meyer, III ,  Steven R. Nickel

    Inventor： Travis R. Hebig ,  Joseph Kuczynski ,  Robert E. Meyer, III ,  Steven R. Nickel

    IPC: H01H37/76 ,  G06F17/50

    CPC classification number: G11C17/18 ,  G06F2201/00 ,  G06F2203/00 ,  G11C17/16 ,  H04W4/00

    Abstract: A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event.

    Abstract translation: 防篡改电子设备包括在电子设备被篡改的每一种情况下单独吹制的多个eFuse。 例如，当电子设备经受导致焊料回流的温度时，eFuse被熔断。 由于预期电子设备可能以可接受的方式和/或可接受的数量的实例被篡改，所以电子设备的功能仅在阈值数量的eFuses被吹制之后被改变或禁用。 在某些实施方案中，阈值数目是预期可接受的篡改事件的数量。 一旦发生篡改事件，个人eFuse就被吹。 如果吹出的eFuse的总数小于阈值，则启用下一个eFuse，以便在下一次篡改事件时可能会被吹。

    Method to optimize random IOS of a storage device for multiple versions of backups using incremental metadata
    20.
    发明授权
    Method to optimize random IOS of a storage device for multiple versions of backups using incremental metadata 有权

    公开(公告)号：US10055420B1

    公开(公告)日：2018-08-21

    申请号：US14788598

    申请日：2015-06-30

    Applicant: EMC Corporation

    Inventor： Prashant Pogde ,  Yamini Allu ,  Mahesh Kamat

    IPC: G06F7/00 ,  G06F17/00 ,  G06F17/30 ,  G06F11/14

    CPC classification number: G06F16/172 ,  G06F11/1448 ,  G06F16/184 ,  G06F16/185 ,  G06F2201/00

    Abstract: Methods, systems, and apparatus for optimizing a cache memory device of a storage system are described. In one embodiment, a first base segment tree representing a first full backup including data and metadata describing the data is cached in a cache memory device. Subsequently, a plurality of incremental segment trees representing incremental backups to the first full backup are cached in the cache memory device. Each of incremental segment trees corresponding to the changes to the first full backup, without modifying the first base segment tree in response to the changes. At least two of the incremental segment trees are merged into an updated incremental segment tree to reduce a storage space of the cache memory device to store the incremental segment trees. The updated incremental segment tree comprises data and metadata represented by two or more incremental segment trees.

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