公开(公告)号：US11923383B2

公开(公告)日：2024-03-05

申请号：US17125836

申请日：2020-12-17

Applicant: Samsung Display Co., Ltd.

Inventor： Dong Hee Shin ,  Geun Ho Lee ,  Yong Hee Lee

IPC: H01L27/12 ,  G03F1/42 ,  G03F1/70 ,  G03F7/00 ,  G03F7/20 ,  H01L23/544

CPC classification number: H01L27/1288 ,  G03F1/42 ,  G03F1/70 ,  G03F7/0007 ,  G03F7/2022 ,  H01L23/544 ,  H01L2223/54493

Abstract: A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

公开(公告)号：US20240053673A1

公开(公告)日：2024-02-15

申请号：US17885870

申请日：2022-08-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chieh CHEN ,  Cheng-Che CHUNG

IPC: G03F1/42 ,  G03F1/44

CPC classification number: G03F1/42 ,  G03F1/44

Abstract: In a layout alignment method of a lithographic system for semiconductor device processing, a reference pattern that is included in a reference pattern module is disposed over an alignment pattern of a substrate. The alignment pattern includes two or more sub-patterns that extend in a first interval along a first direction and are arranged with a first pitch in a second direction. Each sub-pattern includes first patterns and second patterns. A width of the first pattern is at least twice as wide as a width of the second pattern. The reference pattern at least partially overlap with the alignment pattern. An overlay alignment error between the reference pattern and the alignment pattern of the substrate is determined. When the overlay alignment error is not more than a threshold value, a photo resist pattern is produced on the substrate based on the layout pattern associated with reference pattern.

公开(公告)号：US20230387002A1

公开(公告)日：2023-11-30

申请号：US18448125

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Chih-Min HSIAO ,  Ching-Hsu CHANG ,  Jiann-Tyng TZENG

IPC: H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G03F1/42

CPC classification number: H01L23/5226 ,  G06F30/392 ,  G06F30/394 ,  G03F1/42 ,  H01L23/528

Abstract: An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments. Locations of intersections of the first and second tracks define a grid including a first plurality of diagonal grid lines alternating with a second plurality of diagonal grid lines, the first plurality of diagonal grid lines includes at least three via structures of the plurality of via structures positioned at contiguous intersection locations, and the second plurality of diagonal grid lines is free from including a via structure of the plurality of via structures.

公开(公告)号：US20230259017A1

公开(公告)日：2023-08-17

申请号：US18040034

申请日：2020-08-05

Applicant: Nippon Telegraph and Telephone Corporation

Inventor： Takashi Go ,  Ai Yanagihara ,  Keita Yamaguchi ,  Kenya Suzuki

IPC: G03F1/42 ,  G03F9/00 ,  G02B6/13

CPC classification number: G03F1/42 ,  G03F9/7076 ,  G03F9/708 ,  G02B6/13

Abstract: In an optical circuit divided into a plurality of partial circuits, an optical waveguide having a low optical loss at a connection portion is provided. A photomask in which a waveguide pattern of an optical circuit is divided into a plurality of regions and drawn, the photomask including a waveguide pattern for drawing a joint region in which a waveguide width changes as a waveguide goes toward an outer peripheral portion, to connect a plurality of the waveguides divided and drawn to each other, in which the waveguides are connected to each other by overlapping the joint regions of two of the photomasks and performing exposure.

公开(公告)号：US20230236495A1

公开(公告)日：2023-07-27

申请号：US17942339

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Yoshio MIZUTA

IPC: G03F1/42 ,  G03F7/20 ,  G03F9/00

CPC classification number: G03F1/42 ,  G03F7/7055 ,  G03F7/70533 ,  G03F9/7046

Abstract: An exposure apparatus according to an embodiment is configured to implement an exposure process for exposing a substrate to light. The exposure apparatus includes a stage, a storage device, and a controller. The stage is configured to hold the substrate. The storage device is configured to store a plurality of correction maps each having an alignment correction value that differs from each other. The controller is configured to control in the exposure process an exposure position relative to the substrate by selecting a correction map from the correction maps based on measurement results of a plurality of alignment marks arranged on the substrate or an amount of warpage of the substrate and moving the stage based on the selected correction map.

公开(公告)号：US20230194976A1

公开(公告)日：2023-06-22

申请号：US17769054

申请日：2022-04-07

Applicant: KLA Corporation

Inventor： Vladimir Levinski

IPC: G03F1/42 ,  H01L21/027

CPC classification number: G03F1/42 ,  H01L21/0274

Abstract: A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to create an overlay target having a specified geometrical form by using a projection system having a predefined resolution limit to project optical radiation onto the semiconductor substrate through at least one mask. The mask contains target features having target feature dimensions no less than the predefined resolution limit in an arrangement corresponding to the specified geometrical form of the overlay target and assist features interleaved with the target features and having at least one assist feature dimension that is less than the predefined resolution limit.

公开(公告)号：US20180315179A1

公开(公告)日：2018-11-01

申请号：US15908553

申请日：2018-02-28

Applicant: KLA-Tencor Corporation

Inventor： Avner Safrani ,  Ron Rudoi

IPC: G06T7/00 ,  G06T7/73 ,  H01L21/68 ,  G03F1/70

CPC classification number: G06T7/0004 ,  G03F1/42 ,  G03F1/70 ,  G03F7/70741 ,  G06T7/0006 ,  G06T7/73 ,  G06T2207/30148 ,  H01L21/681 ,  H01L21/682

Abstract: A notch detection system receives images of a sample from the imaging detector, in which the sample includes a notched surface and an un-notched surface bounded by a sidewall and further includes at least one notch known notch specifications. The images are generated such that illumination unobstructed by the sample is received by the detector and the sample prevents incident illumination from reaching the detector. The system further determines whether each image includes a notch, identifies the notched surface, and directs a sample positioner to position the sample with the notched surface in a selected direction when a notch is identified in at least one image of the one or more images.

公开(公告)号：US20180267400A1

公开(公告)日：2018-09-20

申请号：US15698025

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Toshiaki KOMUKAI

IPC: G03F1/42 ,  H01L21/027 ,  G03F1/56 ,  G03F1/80

CPC classification number: G03F1/42 ,  G03F1/56 ,  G03F1/80 ,  G03F7/0002 ,  G03F9/7042 ,  H01L21/0272

Abstract: According to an embodiment, a template is provided which includes a template substrate, and a device formation pattern and an alignment mark provided on a common surface of the template substrate. The alignment mark includes a refraction layer provided at a bottom of a first concave pattern provided on the template substrate, and an insulating layer filling the first concave pattern provided with the refraction layer.

公开(公告)号：US20180196348A1

公开(公告)日：2018-07-12

申请号：US15916437

申请日：2018-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-yong JANG ,  Hyung-ho KO ,  Jin-sang YOON

IPC: G03F7/22 ,  G03F1/42 ,  G03F1/32 ,  G03F7/20

CPC classification number: G03F7/22 ,  G03F1/32 ,  G03F1/42 ,  G03F7/203

Abstract: A phase shift mask includes a substrate, a second phase shift pattern on the substrate, the second phase shift pattern extending to an outermost perimeter of the substrate, the second phase shift pattern being formed of a material that is semi-transmissive to light of a first wavelength and the substrate being substantially transparent to the light of the first wavelength such that the mask transmits about 2 to about 10% of the light of the first wavelength at the second phase shift pattern, and a first phase shift pattern on the substrate, the second phase shift pattern being disposed between the outermost perimeter of the substrate and the first phase shift pattern.

公开(公告)号：US09989864B2

公开(公告)日：2018-06-05

申请号：US15325406

申请日：2015-06-11

Applicant: ASML Netherlands B.V.

Inventor： Johannes Jacobus Matheus Baselmans ,  Wilhelmus Petrus De Boeij

IPC: G03B27/42 ,  G03F7/20

CPC classification number: G03F7/70516 ,  G03F1/42 ,  G03F7/70191 ,  G03F7/70775 ,  G03F9/7019 ,  G03F9/7049 ,  G03F9/7088

Abstract: A measurement method including using multiple radiation poles to illuminate a diffraction grating on a mask at a mask side of a projection system of a lithographic apparatus, coupling at least two different resulting diffraction orders per illumination pole through the projection system, using the projection system to project the diffraction orders onto a grating on a wafer such that a pair of combination diffraction orders is formed by diffraction of the diffraction orders, coupling the combination diffraction orders back through the projection system to detectors configured to measure the intensity of the combination diffraction orders, and using the measured intensity of the combination diffraction orders to measure the position of the wafer grating.