公开(公告)号：US20240404877A1

公开(公告)日：2024-12-05

申请号：US18784282

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsai-Ming HUANG ,  Wei-Chieh HUANG ,  Hsun-Chung KUANG ,  Yen-Chang CHU ,  Cheng-Che CHUNG ,  Chin-Wei LIANG ,  Ching-Sen KUO ,  Jieh-Jang CHEN ,  Feng-Jia SHIU ,  Sheng-Chau CHEN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/522 ,  H01L23/544

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

公开(公告)号：US20240053673A1

公开(公告)日：2024-02-15

申请号：US17885870

申请日：2022-08-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chieh CHEN ,  Cheng-Che CHUNG

IPC: G03F1/42 ,  G03F1/44

CPC classification number: G03F1/42 ,  G03F1/44

Abstract: In a layout alignment method of a lithographic system for semiconductor device processing, a reference pattern that is included in a reference pattern module is disposed over an alignment pattern of a substrate. The alignment pattern includes two or more sub-patterns that extend in a first interval along a first direction and are arranged with a first pitch in a second direction. Each sub-pattern includes first patterns and second patterns. A width of the first pattern is at least twice as wide as a width of the second pattern. The reference pattern at least partially overlap with the alignment pattern. An overlay alignment error between the reference pattern and the alignment pattern of the substrate is determined. When the overlay alignment error is not more than a threshold value, a photo resist pattern is produced on the substrate based on the layout pattern associated with reference pattern.

公开(公告)号：US20210327748A1

公开(公告)日：2021-10-21

申请号：US17360784

申请日：2021-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsai-Ming HUANG ,  Wei-Chieh HUANG ,  Hsun-Chung KUANG ,  Yen-Chang CHU ,  Cheng-Che CHUNG ,  Chin-Wei LIANG ,  Ching-Sen KUO ,  Jieh-Jang CHEN ,  Feng-Jia SHIU ,  Sheng-Chau CHEN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/544 ,  H01L23/522

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.