公开(公告)号：US20190057305A1

公开(公告)日：2019-02-21

申请号：US15677311

申请日：2017-08-15

Applicant: Xilinx, Inc.

Inventor： Kristof Denolf ,  Kornelis A. Vissers

IPC: G06N3/08 ,  G06N3/04

Abstract: An example a method of optimizing a neural network having a plurality of layers includes: obtaining an architecture constraint for circuitry of an inference platform that implements the neural network; training the neural network on a training platform to generate network parameters and feature maps for the plurality of layers; and constraining the network parameters, the feature maps, or both based on the architecture constraint.

公开(公告)号：US12067484B2

公开(公告)日：2024-08-20

申请号：US16449264

申请日：2019-06-21

Applicant: Xilinx, Inc.

Inventor： Yaman Umuroglu ,  Nicholas Fraser ,  Michaela Blott ,  Kristof Denolf ,  Kornelis A. Vissers

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084

CPC classification number: G06N3/08 ,  G06N3/063 ,  G06N3/082 ,  G06N3/084

Abstract: An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.

公开(公告)号：US11954359B2

公开(公告)日：2024-04-09

申请号：US17646172

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Kristof Denolf ,  Jack S. Lo ,  Louis Coulon ,  Kornelis A. Vissers

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

公开(公告)号：US20190303033A1

公开(公告)日：2019-10-03

申请号：US15944160

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Tim Tuan ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick

IPC: G06F3/06

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

公开(公告)号：US09711194B2

公开(公告)日：2017-07-18

申请号：US14607978

申请日：2015-01-28

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

IPC: G06F12/02 ,  G06F12/08 ,  G11C7/10 ,  G06F12/0813 ,  G06F13/16

CPC classification number: G11C7/1057 ,  G06F12/0246 ,  G06F12/0813 ,  G06F13/1694 ,  G06F2212/7203 ,  G11C7/1072

Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

公开(公告)号：US09503093B2

公开(公告)日：2016-11-22

申请号：US14260580

申请日：2014-04-24

Applicant: Xilinx, Inc.

Inventor： Kimon Karras ,  Michaela Blott ,  Kornelis A. Vissers

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源，耦合到多个可编程资源的多个可共享逻辑电路和虚拟化电路。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。

公开(公告)号：US20150160862A1

公开(公告)日：2015-06-11

申请号：US14100250

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/466 ,  G06F12/00 ,  G06F13/00 ,  G06F17/30221 ,  G06F17/30312 ,  G06F17/30519

Abstract: A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.

Abstract translation: 描述用于处理数据的电路。 电路包括用于接收实现键值存储数据事务的请求的输入; 与能够访问与键值存储相关联的多个存储器件的不同存储器类型相关联的多个存储器接口; 以及存储器管理电路，其基于数据传输标准，通过多个存储器接口来控制数据的路由。

公开(公告)号：US20230205452A1

公开(公告)日：2023-06-29

申请号：US17646172

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Kristof Denolf ,  Jack S. Lo ,  Louis Coulon ,  Kornelis A. Vissers

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

公开(公告)号：US20230131698A1

公开(公告)日：2023-04-27

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/173

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US11573726B1

公开(公告)日：2023-02-07

申请号：US17097917

申请日：2020-11-13

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick ,  Philip B. James-Roxby

IPC: G06F3/06 ,  G06F15/173 ,  G06F15/78

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.