公开(公告)号：US09960844B1

公开(公告)日：2018-05-01

申请号：US15474588

申请日：2017-03-30

Applicant: Xilinx, Inc.

Inventor： Mayank Raj ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B10/00 ,  H04B10/077 ,  H04B10/60

CPC classification number: H04B10/0775 ,  G01R31/2635 ,  H03K17/78 ,  H04B10/60

Abstract: An example photodiode emulator circuit includes: a first current source circuit; first and second transistors having sources coupled together and coupled to an output of the first current source circuit, a drain of the second transistor coupled to a first node; a third transistor coupled between a drain of the first transistor and a replica load circuit; a second current source circuit coupled to the first node; a capacitor coupled between the first node and electrical ground; and a fourth transistor having a source coupled to the first node and a drain that supplies an output current.

公开(公告)号：US09742597B1

公开(公告)日：2017-08-22

申请号：US15084351

申请日：2016-03-29

Applicant: Xilinx, Inc.

Inventor： Kun-Yung Chang ,  Siok Wei Lim ,  Kee Hian Tan

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/4902 ,  H04L2025/03363 ,  H04L2025/03375 ,  H04L2025/03484 ,  H04L2025/03764

Abstract: An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.

公开(公告)号：US09455848B1

公开(公告)日：2016-09-27

申请号：US14829318

申请日：2015-08-18

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0025 ,  H04L7/0062 ,  H04L7/0087 ,  H04L2025/03611

Abstract: In an example, an apparatus for clock data recovery (CDR) in a receiver includes a decision feedback equalizer (DFE) having a data slicer providing data samples, an error slicer providing error samples, and an offset error slicer providing offset error samples, the offset error slicer operable to set its threshold based on an offset first post-cursor coefficient. The apparatus further includes a CDR circuit operable to control a sampling clock for the data slicer, the error slicer, and the offset error slicer based on the data samples and the offset error samples.

Abstract translation: 在一个示例中，接收机中用于时钟数据恢复（CDR）的装置包括具有提供数据样本的数据限幅器的判定反馈均衡器（DFE），提供误差采样的误差限幅器和提供偏移误差采样的偏移误差限幅器， 偏移误差限幅器，其可操作以基于偏移的第一后置光标系数来设置其阈值。 该装置还包括CDR电路，其可操作以基于数据样本和偏移误差样本来控制数据限幅器，误差限幅器和偏移误差限幅器的采样时钟。

公开(公告)号：US09356775B1

公开(公告)日：2016-05-31

申请号：US14795169

申请日：2015-07-09

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Cheng-Hsiang Hsieh ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/033 ,  H04L7/04

CPC classification number: H04L7/041 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337

Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.

Abstract translation: 描述了用于在时钟和数据恢复（CDR）电路中同步地步进数据相位内插器（PI）代码或交叉PI代码中的至少一个的方法和装置，直到满足一个或多个预设标准。 一个示例性方法通常包括确定已经满足条件; 基于所述确定，在CDR电路中步进每个时钟周期的数据PI代码或交叉PI代码中的至少一个; 基于一个或多个标准停止步进以产生数据PI代码和交叉PI代码的预定状态，其中预定状态包括数据PI代码和交叉PI代码之间的偏移量; 接收数据流; 并且基于数据PI代码和交叉PI代码之间的偏移在数据流上执行时钟和数据恢复。

公开(公告)号：US08736325B1

公开(公告)日：2014-05-27

申请号：US13629377

申请日：2012-09-27

Applicant: Xilinx, Inc.

Inventor： Jafar Savoj ,  Kun-Yung Chang

IPC: H03L7/06

CPC classification number: H03L7/1974

Abstract: A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.

Abstract translation: 一种用于宽频率时钟产生的系统，包括：产生具有频率的信号的锁相环（PLL）; 至少一个小数N分频器来分频信号的频率; 以及多路复用器，用于从PLL接收信号和来自至少一个分数N分频器的输出信号，并且选择来自PLL的信号或来自至少一个小数N分频器的输出信号作为选择的信号。

公开(公告)号：US10749532B1

公开(公告)日：2020-08-18

申请号：US16291286

申请日：2019-03-04

Applicant: Xilinx, Inc.

Inventor： Mayank Raj ,  Didem Z. Turker Melek ,  Parag Upadhyaya ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03L1/02 ,  H03L7/093 ,  H03L7/099 ,  H03L7/07 ,  H03L7/10

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

公开(公告)号：US10291239B1

公开(公告)日：2019-05-14

申请号：US16000698

申请日：2018-06-05

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Winson Lin ,  Parag Upadhyaya ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC: H03L7/08 ,  H03L7/197

Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

公开(公告)号：US09755600B1

公开(公告)日：2017-09-05

申请号：US15049963

申请日：2016-02-22

Applicant: Xilinx, Inc.

Inventor： Didem Z. Turker Melek ,  Parag Upadhyaya ,  Kun-Yung Chang

IPC: H03G3/30 ,  H03F1/02 ,  H03F3/16 ,  H04B1/12

CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/0211 ,  H03F3/16 ,  H03F3/45197 ,  H03F2200/555 ,  H03F2203/45492 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/301 ,  H04B1/123 ,  H04L25/03885

Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.

公开(公告)号：US09325489B2

公开(公告)日：2016-04-26

申请号：US14135071

申请日：2013-12-19

Applicant: Xilinx, Inc.

Inventor： Cheng-Hsiang Hsieh ,  Kun-Yung Chang ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端; 耦合以接收所述数据信号的第一均衡电路，其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路，其中所述第二均衡电路用于调整时钟相位偏移。

公开(公告)号：US09313054B1

公开(公告)日：2016-04-12

申请号：US14617015

申请日：2015-02-09

Applicant: Xilinx, Inc.

Inventor： Yu Liao ,  Hongtao Zhang ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03019 ,  H04L2025/03484

Abstract: A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage coupled to receive digital samples of an input signal. The first stage generates first decision outputs based upon the digital samples. A second stage is coupled to receive the digital samples of the input signal. The second stage comprises a filter receiving the first decision outputs and generating second decision outputs based upon the digital samples of the input signal and detected inter-symbol interference associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.

Abstract translation: 描述用于滤波集成电路中符号间干扰的电路。 电路包括耦合以接收输入信号的数字样本的第一级。 第一阶段基于数字样本产生第一决策输出。 第二级被耦合以接收输入信号的数字样本。 第二级包括接收第一判定输出并基于输入信号的数字样本和检测到的与第一判定输出相关联的符号间干扰的第二判定输出的滤波器。 还描述了一种对集成电路中符号间干扰进行滤波的方法。