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公开(公告)号：US20170033127A1
公开(公告)日：2017-02-02
申请号：US14783870
申请日：2015-08-21
IPC: H01L27/12 , H03K5/135 , H01L27/092 , H03K17/687 , H01L29/786 , H01L29/417
CPC classification number: H01L27/1222 , H01L27/092 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L29/41733 , H01L29/78603 , H01L29/78606 , H01L29/78633 , H01L29/78648 , H01L29/78675 , H03K5/135
Abstract: A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.
Abstract translation: 1.一种薄膜晶体管的控制电路，包括：基板; 设置在所述基板上的氮化硅层; 设置在氮化硅层上的二氧化硅层; 设置在所述氮化硅层内部的遮光层，其包括第一遮光区域和第二遮光区域; 在与所述第一遮光区域对应的位置配置在所述二氧化硅层上的至少一个N型金属氧化物半导体; 在与所述第二遮光区域对应的位置配置在所述二氧化硅层上的至少一个P型金属氧化物半导体; N型金属氧化物半导体和P型金属氧化物半导体中的每一个具有栅电极层，通过栅电极层的电压脉冲接收的第一控制信号与由遮光层接收的电压变化的第二控制信号同步。
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12.发明申请SELF-CAPACITIVE TOUCH PANEL STRUCTURE, IN-CELL TOUCH PANEL, AND LIQUID CRYSTAL DISPLAY 有权自适应触控面板结构，细胞触摸屏和液晶显示公开(公告)号：US20160313844A1
公开(公告)日：2016-10-27
申请号：US14759281
申请日：2015-04-27
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Gui CHEN , Jingfeng XUE
CPC classification number: G06F3/0416 , G02F1/13338 , G06F3/0412 , G06F3/044 , G06F2203/04108 , G06F2203/04111
Abstract: A self-capacitive touch panel structure includes a touch detection chip and multiple self-capacitance electrodes which are isolated with each other and arranged as a matrix. Each self-capacitance electrode is connected with the touch detection chip through a connection line, each self-capacitance electrode is connected with a corresponding connection line through at least one via hole. Wherein, for a same column of the multiple self-capacitance electrodes and according to a sequence of gradually far away from the touch detection chip, a cross-sectional area of a connection line connected with a following self-capacitance electrode is larger than a cross-sectional area of a connection line connected with a previous self-capacitance electrode such that resistance values of the connection lines connected between the self-capacitance electrodes and the touch detection chip are approximately equal. An in-cell touch panel and a liquid crystal display including above structure are also disclosed.
Abstract translation: 自电容式触摸屏结构包括彼此隔离并且被布置为矩阵的触摸检测芯片和多个自身电容电极。 每个自电容电极通过连接线与触摸检测芯片连接，每个自电容电极通过至少一个通孔与相应的连接线连接。 其中，对于多个自电容电极的同一列，并且根据逐渐远离触摸检测芯片的顺序，与随后的自电容电极连接的连接线的横截面积大于十字 与先前的自电容电极连接的连接线的检测区域，使得连接在自身电容电极和触摸检测芯片之间的连接线的电阻值近似相等。 还公开了一种电池内触摸面板和包括上述结构的液晶显示器。
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13.发明申请公开(公告)号：US20180107319A1
公开(公告)日：2018-04-19
申请号：US15841332
申请日：2017-12-14
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Shihpo CHOU , Gui CHEN , Jingfeng XUE
IPC: G06F3/041 , G02F1/1333 , G06F3/044 , G02F1/1343 , G02F1/1362
CPC classification number: G06F3/0412 , G02F1/13338 , G02F1/134336 , G02F1/13439 , G02F1/136286 , G06F3/044
Abstract: A self-capacitive touch panel structure includes a touch detection chip and multiple self-capacitance electrodes arranged as a matrix and isolated with each other. Each self-capacitance electrode connected with the touch detection chip through a connection line. Each self-capacitance electrode electrically connected with a corresponding connection line through at least one via hole. A group of connection lines connected with a same column of the multiple self-capacitance electrodes are divided into an odd number group and an even number group. The connection lines in the odd number group are sequentially connected with a terminal of a corresponding self-capacitance electrode of the same column of the self-capacitance electrodes. The connection lines in the even number group are sequentially connected with a terminal of a corresponding self-capacitance electrode of the same column of the self-capacitance electrodes. An in-cell touch panel and a liquid crystal display including above structure are also disclosed.
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Patent Agency Ranking
公开(公告)号：US20180046044A1
公开(公告)日：2018-02-15
申请号：US14915227
申请日：2016-01-29
Inventor： Yao-li HUANG , Gui CHEN , Jian-hong LIN
IPC: G02F1/1362 , G06F3/041 , G02F1/1333 , G02F1/1368 , G02F1/1335
CPC classification number: G02F1/136204 , G02F1/13338 , G02F1/133514 , G02F1/133528 , G02F1/1368 , G02F2001/133334 , G02F2202/22 , G02F2202/28 , G06F3/0412 , G06F2203/04103 , G06F2203/04107
Abstract: An embedded touch panel and the manufacturing method thereof are disclosed. The embedded touch panel includes a TFT substrate, a liquid crystal layer, a color filter, a polarizer and a glass cover arranged in sequence, wherein the polarizer is a non-conductive polarizer. A transparent conductive layer is arranged between the polarizer and the color filter. The TFT substrate includes at least one grounded pin, and the transparent conductive layer electrically connects with the grounded pin on the TFT substrate. In view of the above, the transparent conductive layer and the non-conductive polarizer may replace the high impedance polarizer of the embedded touch panel so as to greatly reduce the manufacturing cost. In addition, by bonding the frame of the polarizer, the bubble issue occurring when bonding the polarizer may be avoided.
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公开(公告)号：US20170235394A1
公开(公告)日：2017-08-17
申请号：US14904760
申请日：2015-09-28
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Gui CHEN , Caiqin CHEN
IPC: G06F3/047 , G02F1/1333 , G06F3/041
CPC classification number: G06F3/047 , G02F1/1333 , G02F1/13338 , G06F3/0412 , G06F3/0416 , G06F3/044
Abstract: The present invention provides a touch control structure, comprising a touch control zone, and the touch control zone comprises touch control units and first lead wires corresponding to the touch control units, and the touch control units are arranged in array having a plurality of column of the touch control units, and the touch control units of each column are aligned in spaces from top to bottom in the touch control structure, and the first lead wires sequentially penetrate the touch control units in each column from top to bottom in the touch control structure, and the first lead wire is electrically coupled to one touch control unit, and is disconnected with the next touch control unit, which is adjacent to the touch control unit in the same column and close to the top of the touch control structure.
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公开(公告)号：US20170235170A1
公开(公告)日：2017-08-17
申请号：US14902551
申请日：2015-09-23
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Gui CHEN , Caiqin CHEN
IPC: G02F1/1368 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/134309 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F1/136286 , G02F2001/13685 , G02F2201/121 , G02F2201/123 , G02F2201/40 , G02F2202/104 , H01L29/78633
Abstract: The present invention provides a thin film transistor array substrate and a liquid crystal display panel. The thin film transistor array substrate comprises: a substrate; a light shielding layer, located at a middle part on a surface of the substrate; a buffer layer, covering the light shielding layer; a Low Temperature Poly-silicon layer, being located on the buffer layer, and corresponding to the light shielding layer; an isolation layer, covering the Low Temperature Poly-silicon layer, and the isolation layer comprises a through hole, wherein a width of the through hole is smaller than a width of the light shielding layer; a metal layer, located on the isolation layer, and the metal layer is connected with the Low Temperature Poly-silicon layer via the through hole. The thin film transistor array substrate and the liquid crystal display panel have a higher aperture ratio.
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公开(公告)号：US20170222059A1
公开(公告)日：2017-08-03
申请号：US15201439
申请日：2016-07-02
Inventor： Gui CHEN , Qiang GONG
IPC: H01L29/786 , G06F3/044 , G02F1/1343 , G06F3/041 , H01L27/12 , G02F1/1333
CPC classification number: H01L29/78633 , G02F1/13338 , G02F1/134309 , G02F1/136209 , G02F1/136227 , G02F2001/133302 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/044 , G06F2203/04103 , H01L27/1218 , H01L27/1222 , H01L27/124 , H01L27/1262 , H01L29/78618 , H01L29/78675
Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof. The array substrate includes a glass substrate. The shading metal layer and the buffering layer are formed on the glass substrate in sequence. The TFT layer is formed on the buffering layer, and the TFT is arranged above the shading metal layer. The insulation layer and the organic layer are formed on the TFT layer in sequence. In addition, the pixel electrode layer connects to the source/drain of the TFT via the first through hole. The touch electrode layer connects to the shading metal layer via the second through hole. The passivation layer is configured between the pixel electrode layer and the touch electrode layer. In this way, the manufacturing process is simplified, and the coupling capacitance between the touch electrode and the signal line may be effectively reduced.
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公开(公告)号：US20170148921A1
公开(公告)日：2017-05-25
申请号：US14783802
申请日：2015-09-09
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L29/786 , H01L29/66 , H01L29/423
CPC classification number: H01L29/78696 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78645 , H01L29/78675
Abstract: The present invention proposes a TFT, an array substrate, and a method of forming a TFT. The TFT includes a substrate, a buffer layer, a patterned poly-si layer, an isolation layer, a gate layer, and a source/drain pattern layer. The poly-si layer includes a heavily doped source and a heavily doped drain, and a channel. The gate layer includes a first gate area and a second gate area. The source/drain pattern layer includes a source pattern, a drain pattern and a bridge pattern, with the source pattern electrically connecting the heavily doped source, the drain pattern electrically connecting the heavily doped drain, and one end of the bridge pattern connecting the first gate area and the second gate area. The driving ability of the present inventive TFT is enhanced without affecting the leakage current.
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