公开(公告)号：US11791216B2

公开(公告)日：2023-10-17

申请号：US17147134

申请日：2021-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Hsueh-Ju Chen ,  Tsung-Da Lin ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823462 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

公开(公告)号：US20230115634A1

公开(公告)日：2023-04-13

申请号：US17735526

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Co ., Ltd.

Inventor： Tsung-Da Lin ,  Chia-Wei Hsu ,  Chi On Chui

IPC: H01L29/40 ,  H01L29/06 ,  H01L21/28 ,  H01L21/321 ,  H01L29/423

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.

公开(公告)号：US20230378294A1

公开(公告)日：2023-11-23

申请号：US18366410

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chang ,  Te-Yang Lai ,  Kuei-Lun Lin ,  Xiong-Fei Yu ,  Chi On Chui ,  Tsung-Da Lin ,  Cheng-Hao Hou

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0924 ,  H01L2029/7858

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.