公开(公告)号：US20220344489A1

公开(公告)日：2022-10-27

申请号：US17858255

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hsiang Lu ,  Tsung-Han Tsai ,  Shih-Hsun Chang

IPC: H01L29/51 ,  H01L29/45 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02

Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

公开(公告)号：US11024582B2

公开(公告)日：2021-06-01

申请号：US15489905

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ming Chen ,  Yu-Chang Lin ,  Chung-Ting Li ,  Jen-Hsiang Lu ,  Hou-Ju Li ,  Chih-Pin Tsao

IPC: H01L29/76 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

公开(公告)号：US10741654B2

公开(公告)日：2020-08-11

申请号：US15353922

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween.

公开(公告)号：US10672879B2

公开(公告)日：2020-06-02

申请号：US16048833

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Tsai ,  Jen-Hsiang Lu ,  Shih-Hsun Chang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/78

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an isolation feature over a semiconductor substrate. The semiconductor substrate includes a fin structure over the isolation feature. Two opposing spacer elements are formed over the isolation feature and across the fin structure so as to define a gate opening. The gate opening exposes the fin structure and the isolation feature and inner sidewalls of the gate opening have carbon-containing hydrophobic surfaces. A gate structure is formed in the gate opening with the carbon-containing hydrophobic surfaces.

公开(公告)号：US10269968B2

公开(公告)日：2019-04-23

申请号：US14730210

申请日：2015-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jen Chen ,  Chia-Chun Liao ,  Chun-Sheng Liang ,  Shih-Hsun Chang ,  Jen-Hsiang Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

公开(公告)号：US20180301417A1

公开(公告)日：2018-10-18

申请号：US15489905

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ming Chen ,  Yu-Chang Lin ,  Chung-Ting Li ,  Jen-Hsiang Lu ,  Hou-Ju Li ,  Chih-Pin Tsao

IPC: H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

公开(公告)号：US09947756B2

公开(公告)日：2018-04-17

申请号：US15098060

申请日：2016-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Chih-Hao Chang ,  Sheng-Yu Chang ,  Jen-Hsiang Lu ,  Jyun-Yang Shen

IPC: H01L21/764 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417

CPC classification number: H01L29/41791 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.