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公开(公告)号：US20190005990A1
公开(公告)日：2019-01-03
申请号：US15902118
申请日：2018-02-22
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US20140269115A1
公开(公告)日：2014-09-18
申请号：US13873526
申请日：2013-04-30
发明人： Chung-Hsien Hua , Yu-Hao Hsu , Chen-Lin Yang , Cheng Hung Lee
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C11/419 , G11C11/5628
摘要： An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.
摘要翻译： 公开了一种集成驱动器系统。 驱动器系统包括解码逻辑和驱动器部分。 解码逻辑被配置为接收选择信号和数据信号。 驱动器部分被配置为根据解码的信号产生驱动器信号。
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公开(公告)号：US20190004718A1
公开(公告)日：2019-01-03
申请号：US15938502
申请日：2018-03-28
发明人： Yu-Hao HSU , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Hung-Jen Liao , Jung-Ping Yang , Jonathan Tsung-Yung Chang , Wei Min Chan , Yen-Huei Chen , Yangsyu Lin , Chien-Chen Lin
IPC分类号： G06F3/06 , G11C11/4074 , G11C16/12 , G11C16/30 , G11C5/14
摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.
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公开(公告)号：US10510380B2
公开(公告)日：2019-12-17
申请号：US16391986
申请日：2019-04-23
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/687 , H03K17/22
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US20190252008A1
公开(公告)日：2019-08-15
申请号：US16391986
申请日：2019-04-23
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , H03K17/22 , H03K17/687
摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号：US09659603B2
公开(公告)日：2017-05-23
申请号：US14980287
申请日：2015-12-28
发明人： Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
摘要： A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
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