公开(公告)号：US20210083074A1

公开(公告)日：2021-03-18

申请号：US16573334

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

公开(公告)号：US20230386854A1

公开(公告)日：2023-11-30

申请号：US18447943

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG

IPC: H01L21/311 ,  H01J37/32 ,  H01L21/02 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/31122 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32623 ,  H01J37/32724 ,  H01L21/0206 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/6831 ,  H01J37/32422 ,  H01J2237/006 ,  H01J2237/334 ,  H01J2237/335

Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.

公开(公告)号：US20220384599A1

公开(公告)日：2022-12-01

申请号：US17334541

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US20220359503A1

公开(公告)日：2022-11-10

申请号：US17815033

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Chan-Lon YANG ,  Keh-Jeng CHANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US20220199457A1

公开(公告)日：2022-06-23

申请号：US17694158

申请日：2022-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chansyun David YANG ,  Chan-Lon YANG ,  Keh-Jeng CHANG ,  Perng-Fei YUH

IPC: H01L21/687 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/311

Abstract: The present disclosure describes methods and systems for radical-activated etching of a metal oxide. The system includes a chamber, a wafer holder configured to hold a wafer with a metal oxide disposed thereon, a first gas line fluidly connected to the chamber and configured to deliver a gas to the chamber, a plasma generator configured to generate a plasma from the gas, a grid system between the plasma generator and the wafer holder and configured to increase a kinetic energy of ions from the plasma, a neutralizer between the grid system and the wafer holder and configured to generate electrons and neutralize the ions to generate radicals, and a second gas line fluidly connected to the chamber and configured to deliver a precursor across the wafer. The radicals facilitate etching of the metal oxide by the precursor.

公开(公告)号：US20220037163A1

公开(公告)日：2022-02-03

申请号：US16944653

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/02 ,  H01J37/32

Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.

公开(公告)号：US20230395685A1

公开(公告)日：2023-12-07

申请号：US18231486

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/1037 ,  H01L29/0673

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US20230031722A1

公开(公告)日：2023-02-02

申请号：US17383962

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01J37/08 ,  H01L21/311 ,  H01J37/32

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a process chamber. The process chamber includes a plasma chamber configured to provide plasma. In addition, the process chamber includes an accelerator grid having multiple accelerator grid elements including a first accelerator grid element and a second accelerator grid element. A first wire is coupled to the first accelerator grid element and configured to supply a first voltage to the first accelerator grid element. A second wire is coupled to the second accelerator grid element and configured to supply a second voltage to the second accelerator grid element, where the second voltage is different from the first voltage. A first ion beam through a first hole is controlled by the first accelerator grid element, and a second ion beam through a second hole is controlled by the second accelerator grid element.

公开(公告)号：US20220270935A1

公开(公告)日：2022-08-25

申请号：US17663608

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG

IPC: H01L21/84 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

公开(公告)号：US20210376137A1

公开(公告)日：2021-12-02

申请号：US16885850

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.