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    Logic Compatible RRAM Structure and Process
    11.
    发明申请
    Logic Compatible RRAM Structure and Process 审中-公开

    公开(公告)号：US20200381622A1

    公开(公告)日：2020-12-03

    申请号：US16994359

    申请日：2020-08-14

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

    IPC: H01L45/00

    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

    Logic compatible RRAM structure and process
    12.
    发明授权
    Logic compatible RRAM structure and process 有权

    公开(公告)号：US10749108B2

    公开(公告)日：2020-08-18

    申请号：US16217134

    申请日：2018-12-12

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

    IPC: H01L45/00

    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

    Resistance variable memory structure
    13.
    发明授权
    Resistance variable memory structure 有权

    公开(公告)号：US10103330B2

    公开(公告)日：2018-10-16

    申请号：US15811249

    申请日：2017-11-13

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Chin-Chieh Yang ,  Wen-Ting Chu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.

    One Transistor and One Resistive Random Access Memory (RRAM) Structure with Spacer
    16.
    发明申请
    One Transistor and One Resistive Random Access Memory (RRAM) Structure with Spacer 审中-公开
    一个晶体管和一个电阻随机存取存储器（RRAM）结构与间隔器

    公开(公告)号：US20160248008A1

    公开(公告)日：2016-08-25

    申请号：US15144639

    申请日：2016-05-02

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Chin-Chieh Yang ,  Chih-Yang Chang ,  Yu-Wen Liao

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1246 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

    Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

    Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和顶部部分的底部电极，底部电极上的电阻材料层具有与底部电极的顶部部分的宽度相同的宽度; 底部电极上的覆盖层; 包围覆盖层的间隔物; 并且所述覆盖层上的顶部电极具有比所述电阻材料层更小的宽度。 RRAM单元还包括将RRAM结构的顶部电极连接到金属层的导电材料。

    Resistance variable memory structure and method of forming the same
    17.
    发明授权
    Resistance variable memory structure and method of forming the same 有权
    电阻变量记忆结构及其形成方法

    公开(公告)号：US09312482B2

    公开(公告)日：2016-04-12

    申请号：US13896064

    申请日：2013-05-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Chin-Chieh Yang ,  Wen-Ting Chu

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1675

    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.

    Abstract translation: 半导体结构包括存储区。 存储器结构设置在存储器区域上。 存储结构包括第一电极，电阻变化层，保护材料和第二电极。 第一电极在存储区域上具有顶表面。 电阻变化层具有至少第一部分和第二部分。 第一部分设置在第一电极的顶表面上，第二部分从第一部分向上延伸。 保护材料围绕电阻变化层的第二部分。 保护材料可配置为保护电阻变化层中的至少一个导电路径。 第二电极设置在电阻变化层上。

    Resistance variable memory structure
    18.
    发明授权
    Resistance variable memory structure 有权
    电阻变量记忆结构

    公开(公告)号：US08921818B2

    公开(公告)日：2014-12-30

    申请号：US13673658

    申请日：2012-11-09

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Chi Tu ,  Wen-Ting Chu ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Hsia-Wei Chen ,  Chih-Yang Chang

    IPC: H01L47/00 ,  G11C11/00 ,  H01L45/00

    CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1691

    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.

    Abstract translation: 半导体结构包括电阻变化存储器结构。 半导体结构还包括电介质层。 电阻可变存储器结构在电介质层之上。 电阻可变存储器结构包括设置在电介质层上的第一电极。 第一电极具有侧壁表面。 电阻变化层具有设置在第一电极的侧壁表面上的第一部分和从第一部分延伸离开第一电极的第二部分。 第二电极在电阻变化层之上。

    Method for Operating RRAM Memory
    19.
    发明申请
    Method for Operating RRAM Memory 有权
    操作RRAM内存的方法

    公开(公告)号：US20140254237A1

    公开(公告)日：2014-09-11

    申请号：US13788063

    申请日：2013-03-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Chia-Fu Lee

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0097 ,  G11C2213/79

    Abstract: Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory (RRAM) cell; applying a first programming voltage to a source line node of the first RRAM cell; and setting the first RRAM cell comprising applying a second programming voltage to a bit line node of the first RRAM cell. The first programming voltage is greater than zero volts, and the second programming voltage is greater than the first programming voltage. Other disclosed methods include concurrently setting and resetting RRAM cells.

    Abstract translation: 公开了操作存储器的方法。 一种方法包括：将选择字线电压施加到第一电阻随机存取存储器（RRAM）单元的字线节点; 将第一编程电压施加到所述第一RRAM单元的源极线节点; 以及设置所述第一RRAM单元包括将第二编程电压施加到所述第一RRAM单元的位线节点。 第一编程电压大于零伏，第二编程电压大于第一编程电压。 其他公开的方法包括同时设置和重置RRAM单元。

    Logic compatible RRAM structure and process
    20.
    发明授权
    Logic compatible RRAM structure and process 有权
    逻辑兼容的RRAM结构和过程

    公开(公告)号：US08742390B1

    公开(公告)日：2014-06-03

    申请号：US13674193

    申请日：2012-11-12

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang

    IPC: H01L47/00 ,  G11C11/00

    CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/122 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

    Abstract: A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

    Abstract translation: 一种存储单元和方法，包括通过第一电介质层中的第一开口保形地形成的第一电极，保形地形成在第一电极上的电阻层，保形地形成在电阻层上的第二电极和保形地形成在第一电介质层上的第二电介质层 第二电极，第二介电层包括第二开口。 第一介电层形成在包括第一金属层的基板上。 第一电极和电阻层共同地包括第一距离超过由第一开口限定的区域延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过由第一开口限定的区域的第二唇缘区域。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。

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