公开(公告)号：US11871558B2

公开(公告)日：2024-01-09

申请号：US17963591

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jae Hoon Kim ,  Kwang-ho Park ,  Seungjae Jung

IPC: H01L29/786 ,  H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

CPC classification number: H10B12/30 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/01 ,  H10B12/05 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US11751379B2

公开(公告)日：2023-09-05

申请号：US17731611

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon Kim ,  Kwang-Ho Park ,  Yong-Hoon Son ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

IPC: G11C5/06 ,  H10B12/00 ,  G11C11/4097

CPC classification number: H10B12/30 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US11751378B2

公开(公告)日：2023-09-05

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Kiseok Lee ,  Seungjae Jung ,  Joongchan Shin ,  Taehyun An ,  Moonyoung Jeong ,  Sangyeon Han

IPC: H10B12/00 ,  H01L29/08

CPC classification number: H10B12/30 ,  H01L29/0847 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US11502086B2

公开(公告)日：2022-11-15

申请号：US17038355

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon Son ,  Jae Hoon Kim ,  Kwang-Ho Park ,  Seungjae Jung

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US11462554B2

公开(公告)日：2022-10-04

申请号：US16857507

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jae Hoon Kim ,  Kwang-ho Park ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

IPC: H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US11410951B2

公开(公告)日：2022-08-09

申请号：US17207242

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun Choi ,  Eun-Ji Kim ,  Jong-Ho Moon ,  Hyoungyol Mun ,  Han-Sik Yoo ,  Kiseok Lee ,  Seungjae Jung ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C11/408 ,  H01L25/065 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

公开(公告)号：US11348924B2

公开(公告)日：2022-05-31

申请号：US16923572

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon Kim ,  Kwang-Ho Park ,  Yong-Hoon Son ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

IPC: G11C5/06 ,  H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.