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    CAPACITOR STRUCTURE
    12.
    发明申请
    CAPACITOR STRUCTURE 有权

    公开(公告)号：US20250048617A1

    公开(公告)日：2025-02-06

    申请号：US18736153

    申请日：2024-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： BYEUNGMOO KANG ,  SEOKHAN PARK ,  KISEOK LEE

    IPC: H10B12/00

    Abstract: A capacitor structure may include a plurality of lower electrodes arranged in a first direction and a second direction perpendicular to the first direction, a supporter including a plurality of openings and adjoining the plurality of lower electrodes, a dielectric layer covering the supporter and the plurality of lower electrodes, and an upper electrode covering the dielectric layer, where each of the plurality of openings contacts four lower electrodes, and where the plurality of openings contact opposite sides of the plurality of lower electrodes along the first direction and the second direction.

    SEMICONDUCTOR MEMORY DEVICE
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220246180A1

    公开(公告)日：2022-08-04

    申请号：US17481583

    申请日：2021-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

    IPC: G11C5/06 ,  H01L29/06 ,  H01L27/108

    Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210296237A1

    公开(公告)日：2021-09-23

    申请号：US17097337

    申请日：2020-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HYO-SUB KIM ,  SOHYUN PARK ,  DAEWON KIM ,  DONGOH KIM ,  EUN A KIM ,  CHULKWON PARK ,  TAEJIN PARK ,  KISEOK LEE ,  SUNGHEE HAN

    IPC: H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L21/768

    Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

    SEMICONDUCTOR DEVICE
    18.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240107743A1

    公开(公告)日：2024-03-28

    申请号：US17953054

    申请日：2022-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNHYEOK AHN ,  KISEOK LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10897

    Abstract: A semiconductor device includes; a substrate including an active region including a first region and a second region, a bitline extending in a first direction on the substrate and electrically connected to the first region of the active region, a spacer structure disposed on a side surface of the bitline, a contact structure disposed on a side surface of the spacer structure and electrically connected to the second region of the active region and a data storage structure disposed on the contact structure and electrically connected to the contact structure. The contact structure includes; a conductive contact layer including a first portion and a second portion disposed on the first portion, a barrier layer surrounding the first portion of the conductive contact layer, and an air gap surrounding the second portion of the conductive contact layer.

    SEMICONDUCTOR MEMORY DEVICE
    19.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230397430A1

    公开(公告)日：2023-12-07

    申请号：US18303854

    申请日：2023-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KISEOK LEE ,  KEUNNAM KIM ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  KYUNGHWAN LEE

    IPC: H10B51/30 ,  H10B51/20

    CPC classification number: H10B51/30 ,  H10B51/20

    Abstract: A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE
    20.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE 审中-公开

    公开(公告)号：US20230389310A1

    公开(公告)日：2023-11-30

    申请号：US17994175

    申请日：2022-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KEUNNAM KIM ,  KISEOK LEE ,  BYEONGJOO KU

    IPC: H10B41/40 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/40 ,  H10B43/20 ,  H01L23/528

    CPC classification number: H01L27/11526 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11578 ,  H01L23/5283

    Abstract: A semiconductor memory device includes; a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.

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