公开(公告)号：US11115021B2

公开(公告)日：2021-09-07

申请号：US17021728

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

公开(公告)号：US20240321330A1

公开(公告)日：2024-09-26

申请号：US18611213

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anil KAVALA ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C7/22 ,  G11C7/14 ,  H03L7/099

CPC classification number: G11C7/222 ,  G11C7/14 ,  H03L7/0998

Abstract: A storage device includes a buffer chip and a memory device. The memory device transmits a random data signal and a data strobe signal to the buffer chip based on a clock signal received from the buffer chip. The buffer chip includes a delay circuit that delays the data strobe signal by a delay time to generate a delayed data strobe signal, a sampler that receives the delayed data strobe signal from the delay circuit and samples the random data signal based on the delayed data strobe signal to generate sampled data, a comparator that compares internal data with the sampled data to generate a comparison result, and a counter module that receives the comparison result from the comparator and determines a target delay based on the comparison result. The buffer chip delays the delayed data strobe signal based on the target delay.

公开(公告)号：US20240312551A1

公开(公告)日：2024-09-19

申请号：US18529619

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/38

CPC classification number: G11C29/46 ,  G11C29/1201 ,  G11C29/38 ,  G11C2029/4002

Abstract: A storage device includes a plurality of memory chips, a buffer chip connected to the plurality of memory chips, and a controller connected to the buffer chip. The buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command. At least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.

公开(公告)号：US11984170B2

公开(公告)日：2024-05-14

申请号：US18160620

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon

IPC: G11C16/32 ,  G11C16/04 ,  H01L25/065

CPC classification number: G11C16/32 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06506

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

公开(公告)号：US11502687B2

公开(公告)日：2022-11-15

申请号：US17389148

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

公开(公告)号：US11309033B2

公开(公告)日：2022-04-19

申请号：US17121015

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Youngmin Jo ,  Seungwon Lee

IPC: G11C16/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11582

Abstract: A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.

公开(公告)号：US11163453B2

公开(公告)日：2021-11-02

申请号：US17027978

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Daeseok Byeon ,  Tongsung Kim

IPC: G06F3/06 ,  G06N3/08 ,  G06F12/02

Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O pins connected to the second channel group, wherein the memory area includes at least one memory chip, wherein the at least one memory chip includes a first chip having a first metal pad and a cell region and a second chip having a second metal pad and a peripheral circuit region, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US12210773B2

公开(公告)日：2025-01-28

申请号：US17528285

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Seonkyoo Lee ,  Byunghoon Jeong

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K19/00 ,  H10B43/27

Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

公开(公告)号：US12073917B2

公开(公告)日：2024-08-27

申请号：US17404510

申请日：2021-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Manjae Yang ,  Chiweon Yoon ,  Junha Lee ,  Byunghoon Jeong

IPC: G06F1/04 ,  G06F3/06 ,  G11C7/22 ,  G11C29/02 ,  G11C5/14

CPC classification number: G11C7/222 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C29/023 ,  G11C29/028 ,  G11C5/145

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US11810638B2

公开(公告)日：2023-11-07

申请号：US17410210

申请日：2021-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonkyoo Lee ,  Chiweon Yoon ,  Byunghoon Jeong ,  Youngmin Jo

IPC: G11C7/10 ,  H01L25/065 ,  G06F13/42

CPC classification number: G11C7/1048 ,  H01L25/0657 ,  G06F13/4282 ,  G11C2207/12 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.