公开(公告)号：US09905285B2

公开(公告)日：2018-02-27

申请号：US15249333

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Cho ,  Jaegeun Park ,  Youngkwang Yoo

IPC: G11C7/00 ,  G06F9/00 ,  G11C11/4074 ,  G11C11/406 ,  G06F1/32

CPC classification number: G11C11/4074 ,  G06F1/3287 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a plurality of memory cells, a refresh controller configured to perform a plurality of refresh operations on the plurality of memory cells in response to a plurality of refresh commands from an external device, and a refresh counter configured to count a number of the refresh commands for a fixed period of time and compare the counted number with a threshold. The refresh counter is configured to generate a power failure signal to cause the DRAM device to enter a power failure mode in response to the comparison of the counted number with the threshold. The refresh controller is configured to perform a refresh operation on the plurality of memory cells without control of the external device in the power failure mode.

公开(公告)号：US11669393B2

公开(公告)日：2023-06-06

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Youngkwang Yoo ,  Younggeun Lee ,  Yena Lee

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

CPC classification number: G06F11/1044 ,  G06F9/30029 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0246 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US11537471B2

公开(公告)日：2022-12-27

申请号：US17469377

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US11507460B2

公开(公告)日：2022-11-22

申请号：US17448995

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US11163638B2

公开(公告)日：2021-11-02

申请号：US16695395

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Youngkwang Yoo ,  Younggeun Lee ,  Yena Lee

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US10649894B2

公开(公告)日：2020-05-12

申请号：US16195533

申请日：2018-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Ju Lee ,  Youngjin Cho ,  Sungyong Seo ,  Youngkwang Yoo

IPC: G06F12/02 ,  G06F13/42 ,  G06F12/06 ,  G06F13/16 ,  G06F3/06

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.

公开(公告)号：US09824777B2

公开(公告)日：2017-11-21

申请号：US14796533

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Jaegeun Park ,  Youngkwang Yoo ,  Biwoong Chung

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/54

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

Abstract: A storage system is provided which includes: a storage device including a first memory, which may be nonvolatile memory, and a second memory, which may be a device memory, and configured to request a test on at least one of the first and second memories; and a host configured to test the at least one memory in response to the request for the memory test from the storage device and store the test result in the first memory or a third memory.