公开(公告)号：US10949094B2

公开(公告)日：2021-03-16

申请号：US16298318

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Ju Lee ,  Youngkwang Yoo ,  Youngjin Cho

IPC: G06F3/06 ,  G06F13/38

Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.

公开(公告)号：US11742046B2

公开(公告)日：2023-08-29

申请号：US17318234

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongho Lee ,  Kwangjin Lee ,  Hee Hyun Nam ,  Jaeho Shin ,  Youngkwang Yoo

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18

CPC classification number: G11C29/42 ,  G11C7/1012 ,  G11C7/1063 ,  G11C29/18 ,  G11C29/44

Abstract: Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.

公开(公告)号：US10203909B2

公开(公告)日：2019-02-12

申请号：US15421514

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkwang Yoo ,  Youngjin Cho ,  Han-Ju Lee ,  JinHyeok Choi

IPC: G06F3/06 ,  G11C8/12 ,  G06F12/0868

Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

公开(公告)号：US11216394B2

公开(公告)日：2022-01-04

申请号：US16411330

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Ju Lee ,  Youngkwang Yoo ,  Youngjin Cho

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

公开(公告)号：US10324869B2

公开(公告)日：2019-06-18

申请号：US15260916

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Ju Lee ,  Youngkwang Yoo ,  Youngjin Cho

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

公开(公告)号：US20160357462A1

公开(公告)日：2016-12-08

申请号：US15096877

申请日：2016-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Hyun Nam ,  Jaegeun Park ,  Sungyong Seo ,  Youngkwang Yoo ,  Han-Ju Lee ,  Youngjin Cho

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

Abstract: Disclosed is a nonvolatile memory module. The nonvolatile memory module includes at least one nonvolatile memory, a random access memory (RAM) and a device controller. Responsive to receiving a write request comprising sub-data from a host, the device controller accumulates the sub-data in the RAM and programs the accumulated sub-data in the nonvolatile memory. A size of the sub-data is smaller than a size of a default transmission unit provided from the host.

Abstract translation: 公开了一种非易失性存储器模块。 非易失性存储器模块包括至少一个非易失性存储器，随机存取存储器（RAM）和器件控制器。 响应于从主机接收到包含子数据的写入请求，设备控制器将该子数据累加在RAM中，并将累积的子数据编程在非易失性存储器中。 子数据的大小小于从主机提供的默认传输单元的大小。

公开(公告)号：US11847024B2

公开(公告)日：2023-12-19

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US11144393B2

公开(公告)日：2021-10-12

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US10261697B2

公开(公告)日：2019-04-16

申请号：US15055689

申请日：2016-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Ju Lee ,  Youngkwang Yoo ,  Youngjin Cho

IPC: G06F3/06

Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.

公开(公告)号：US10152413B2

公开(公告)日：2018-12-11

申请号：US15083425

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Ju Lee ,  Youngjin Cho ,  Sungyong Seo ,  Youngkwang Yoo

IPC: G06F12/02 ,  G06F13/42 ,  G06F12/06

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.