公开(公告)号：US11257905B2

公开(公告)日：2022-02-22

申请号：US16386459

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Seung Hun Lee ,  Su Jin Jung ,  Young Dae Cho

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/82 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

公开(公告)号：US20250056789A1

公开(公告)日：2025-02-13

申请号：US18620333

申请日：2024-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jin Nam ,  Sung-Hwan Jang ,  Won Hee Choi ,  Sung Uk Jang

IPC: H10B12/00

Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device comprises a substrate, a structure including word lines and interlayer insulating films alternately stacked on the substrate, a channel region disposed between two adjacent word lines in a vertical direction, a first source/drain region disposed on a first side of the channel region, a second source/drain region disposed on a second side of the channel region, a bit line which extends in the vertical direction on the substrate and is connected to the first source/drain region, a capping insulating film disposed between the bit line and the word lines, and a data storage connected to the second source/drain region. At least a part of the first source/drain region protrudes from a sidewall of the capping insulating film toward the bit line.

公开(公告)号：US11916123B2

公开(公告)日：2024-02-27

申请号：US17383022

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Dae Cho ,  Ki Hwan Kim ,  Sung Uk Jang ,  Su Jin Jung

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0847 ,  H01L29/78696

Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.

公开(公告)号：US11901453B2

公开(公告)日：2024-02-13

申请号：US17587402

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Ki Hwan Kim ,  Su Jin Jung ,  Bong Soo Kim ,  Young Dae Cho

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L21/02521 ,  H01L21/02603 ,  H01L21/02636 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US11594598B2

公开(公告)日：2023-02-28

申请号：US17546326

申请日：2021-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Seung Hun Lee ,  Su Jin Jung ,  Young Dae Cho

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.