公开(公告)号：US12199056B2

公开(公告)日：2025-01-14

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Unbyoung Kang ,  Byeongchan Kim ,  Solji Song ,  Chungsun Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US20240162104A1

公开(公告)日：2024-05-16

申请号：US18462010

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsu Hwang ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3107 ,  H01L21/78 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: A semiconductor device may include a substrate, one or more front pads disposed on a front surface of the substrate, and a circuit layer including an insulating layer and at least one interconnection electrically connected to the one or more front pads. In some embodiments, the circuit layer may be disposed between the one or more front pads and the substrate. In some embodiments, a side surface of the circuit layer may include a burr that protrudes a height that is below a level of a front surface of the circuit layer. Additionally or alternatively, the burr may form a step portion in the circuit layer.

公开(公告)号：US20230420397A1

公开(公告)日：2023-12-28

申请号：US18322570

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Hyunchul Jung

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/48 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/05082 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05025

Abstract: A includes a semiconductor substrate, a pad insulating layer disposed on the semiconductor substrate, a through electrode structure that partially penetrates the semiconductor substrate but does not penetrate the pad insulating layer, an insulating liner that at least partially surrounds the through electrode structure, an insulating sidewall that penetrates the pad insulating layer, a part of the semiconductor substrate and at least a part of the insulating liner, and includes a pad hole formed therein, and a bonding pad structure disposed on the pad insulating layer and that fills the pad hole, and contacts the through electrode structure

公开(公告)号：US11854893B2

公开(公告)日：2023-12-26

申请号：US17850714

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/0206 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/97

Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

公开(公告)号：US11538783B2

公开(公告)日：2022-12-27

申请号：US17088350

申请日：2020-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US11476176B2

公开(公告)日：2022-10-18

申请号：US17035145

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC: H01L29/40 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/321 ,  H01L23/29 ,  H01L21/3105

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.