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11.发明申请公开(公告)号：US20220171913A1
公开(公告)日：2022-06-02
申请号：US17380200
申请日：2021-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sooyong Lee , Jeeyong Lee , Seunghune Yang , Hyeyoung Ji
IPC: G06F30/398 , G06N20/00
Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.
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公开(公告)号：US09672611B2
公开(公告)日：2017-06-06
申请号：US14693914
申请日：2015-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiho Yang , Kaiyuan Chi , Seunghune Yang , Sibo Cai
CPC classification number: G06T7/001 , G01N23/20 , G01N23/2251 , G06T2207/10061 , G06T2207/30148 , H01J37/222 , H01J37/28 , H01J2237/24592 , H01J2237/2816 , H01J2237/2817 , H01L22/12
Abstract: A pattern analysis method of a semiconductor device includes extracting a contour image of material layer patterns formed on a wafer, calculating an individual density value (DV) representing an area difference between the contour image and a target layout image, scoring the material layer patterns on the wafer using the individual DV, identifying a failure pattern among the scored material layer patterns, calculating coordinates of the identified failure pattern and displaying the coordinates on a critical dimension-scanning electron microscopy (CD-SEM) image, inputting a reference DV in the computer and automatically sorting the material layer patterns into material layer patterns having a hotspot and material layer patterns not having a hotspot, and reviewing the sorted material layer patterns having the hotspot.
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Patent Agency Ranking
13.发明授权公开(公告)号：US12086526B2
公开(公告)日：2024-09-10
申请号：US17380200
申请日：2021-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sooyong Lee , Jeeyong Lee , Seunghune Yang , Hyeyoung Ji
IPC: G06F30/398 , G06N20/00
CPC classification number: G06F30/398 , G06N20/00
Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.
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14.发明授权公开(公告)号：US11900043B2
公开(公告)日：2024-02-13
申请号：US17701520
申请日：2022-03-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sooyong Lee , Dongho Kim , Sangwook Kim , Jungmin Kim , Seunghune Yang , Jeeyong Lee , Changmook Yim , Yangwoo Heo
IPC: G06F30/30 , G03F7/00 , G06F30/398 , G06F30/392 , G06F30/27 , G06F119/18
CPC classification number: G06F30/398 , G03F7/705 , G03F7/70441 , G06F30/27 , G06F30/392 , G06F2119/18
Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.
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公开(公告)号：US20230253179A1
公开(公告)日：2023-08-10
申请号：US17935128
申请日：2022-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUNG MIN NAM , Jaeseung Jeong , Dongho Kim , Seunghune Yang
CPC classification number: H01J37/28 , H01J37/222 , H01L22/12 , G01B11/02 , H01J2237/2817 , H01J2237/223 , H01J2237/226 , G01B2210/56
Abstract: A pitch walk inspection method includes obtaining a scanning electron microscope (SEM) image for a line and space (L/S) pattern formed by a multi-patterning technology (MPT), where L/S pattern includes a plurality of lines and spaces that are alternately arranged; detecting a main pitch of the L/S pattern in the SEM image; dividing a graph of the main pitch into graphs of component pitches, based on the MPT; performing a Fast Fourier Transform (FFT) on each graph of the component pitches; multiplying a phase and an intensity graph of the FFT of each of the graphs of the component pitches with each other and obtaining compensated FFT phase graphs; and calculating a pitch walk for the L/S pattern by obtaining differences between phase peak values of the compensated FFT phase graphs.
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16.发明授权公开(公告)号：US09965851B2
公开(公告)日：2018-05-08
申请号：US15051814
申请日：2016-02-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kaiyuan Chi , Kiho Yang , Seunghune Yang
CPC classification number: G06T7/001 , G06K9/4604 , G06K9/685 , G06K2209/19 , G06T7/11 , G06T7/12 , G06T7/155 , G06T2207/10061 , G06T2207/30148 , G06T2207/30172 , H01L22/12
Abstract: The inventive concepts provide a method for inspecting a pattern, a method for manufacturing a semiconductor device, and an apparatus used according to the methods. The method for inspecting a pattern includes detecting a measured image corresponding to a pattern formed on a substrate, detecting a first hot spot corresponding to a ghost image of the measured image, with the first hot spot representing a defect of the pattern, and detecting a second hot spot that has an area that is wider than that of the first hot spot.
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17.发明申请METHOD FOR INSPECTING PATTERN AND AN APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 有权用于检查图案的方法和使用其制造半导体器件的装置公开(公告)号：US20160275663A1
公开(公告)日：2016-09-22
申请号：US15051814
申请日：2016-02-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kaiyuan Chi , Kiho Yang , Seunghune Yang
CPC classification number: G06T7/001 , G06K9/4604 , G06K9/685 , G06K2209/19 , G06T7/11 , G06T7/12 , G06T7/155 , G06T2207/10061 , G06T2207/30148 , G06T2207/30172 , H01L22/12
Abstract: The inventive concepts provide a method for inspecting a pattern, a method for manufacturing a semiconductor device, and an apparatus used according to the methods. The method for inspecting a pattern includes detecting a measured image corresponding to a pattern formed on a substrate, detecting a first hot spot corresponding to a ghost image of the measured image, with the first hot spot representing a defect of the pattern, and detecting a second hot spot that has an area that is wider than that of the first hot spot.
Abstract translation: 本发明构思提供了用于检查图案的方法，用于制造半导体器件的方法以及根据该方法使用的装置。 检查图案的方法包括检测与形成在基板上的图案相对应的测量图像，检测与测量图像的重影图像相对应的第一热点，第一热点表示图案的缺陷，并且检测 第二个热点的面积比第一个热点高。
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