公开(公告)号：US20170301392A1

公开(公告)日：2017-10-19

申请号：US15639073

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C11/4093 ,  G11C11/408 ,  G11C7/10 ,  H01L25/065 ,  H01L27/108 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

公开(公告)号：US09721644B2

公开(公告)日：2017-08-01

申请号：US15207989

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C5/02 ,  G11C11/4093 ,  H01L27/108 ,  H01L25/065 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

公开(公告)号：US09041222B2

公开(公告)日：2015-05-26

申请号：US14487287

申请日：2014-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon Kim ,  Keung Beum Kim ,  Seongho Shin ,  Seung-Yong Cha ,  Inho Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Abstract translation: 提供一种半导体器件，其包括第一半导体封装，第二半导体封装和连接结构。 第一半导体封装包括第一衬底。 第一基板包括第一区域和第二区域。 第二半导体封装安装在第一半导体封装上。 连接结构电连接第二半导体封装和第一半导体封装。 连接结构包括在第一区域的第一连接图案。 第一连接图案在第一区域提供数据信号。 连接结构还包括在第二区域处的第二连接图案。 第二连接模式在第二区域提供控制/寻址信号。 多个第二连接图案小于第一连接图案的数量。