公开(公告)号：US20230200053A1

公开(公告)日：2023-06-22

申请号：US17945235

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Sunghyun Park ,  Jinyoung Park ,  Minkyu Suh ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/033

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

公开(公告)号：US20230171954A1

公开(公告)日：2023-06-01

申请号：US17965936

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Namgun Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Minkyu Suh ,  Jungpyo Hong

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: A semiconductor device includes a substrate having a cell array region and a peripheral region, lower electrodes disposed on the cell array region, at least one supporter layer contacting the lower electrodes, a dielectric layer covering the lower electrodes and the at least one supporter layer, an upper electrode covering the dielectric layer, an interlayer insulating layer covering an upper surface and a side surface of the upper electrode, a peripheral contact plug passing through the interlayer insulating layer on the peripheral region of the substrate, and a first oxide layer between the upper electrode and the peripheral contact plug. The upper electrode includes at least one protruding region protruding in a lateral direction from the cell array region toward the peripheral region. The first oxide layer is disposed between the at least one protrusion region and the peripheral contact plug.

公开(公告)号：US20230094529A1

公开(公告)日：2023-03-30

申请号：US17807146

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINYOUNG PARK ,  Sangwuk Park ,  Hyun-Chul Yoon ,  Jungpyo Hong

IPC: H01L27/108

Abstract: A semiconductor memory device includes active sections that include first and second impurity regions and are defined by a device isolation layer. Word lines extend in a first direction on the active sections. Intermediate dielectric patterns cover top surfaces of the word lines. Bit-line structures extend on the word lines in a second direction intersecting the first direction. Contact plugs are disposed between the bit-line structures and are connected to the second impurity regions. Data storage elements are disposed on the contact plugs. The intermediate dielectric pattern includes a capping part that covers the top surfaces of the word lines and is buried in the substrate. Fence parts extend between the bit-line structures from the capping part.

公开(公告)号：US20230084694A1

公开(公告)日：2023-03-16

申请号：US17735306

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANMI LEE ,  Sangwuk Park ,  Yejeong Seo ,  Sanggyo Chung

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/528

Abstract: A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.

公开(公告)号：US20190296018A1

公开(公告)日：2019-09-26

申请号：US16185892

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.