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    WIRING BOARD AND SEMICONDUCTOR PACKAGE
    12.
    发明申请
    WIRING BOARD AND SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230127676A1

    公开(公告)日：2023-04-27

    申请号：US17858441

    申请日：2022-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangwook Park ,  Sangnam Jeong

    IPC: H01L23/66 ,  H01L23/498 ,  H01L25/065

    Abstract: A semiconductor package includes a wiring board including at least one pair of connection structures electrically connecting at least one pair of differential signal transmission lines and at least one pair of differential signal transmission terminals, respectively. The at least one pair of connection structures includes first via structures staggered in a vertical direction, at least one first connection line electrically connecting the first via structures, second via structures staggered in the vertical direction, and at least one second connection line electrically connecting the second via structures. The at least one first connection line is spaced apart from the at least one second connection line in the vertical direction and electrically insulated therefrom, and intersects the at least one second connection line in the vertical direction.

    Method of fabricating a photomask
    13.
    发明授权
    Method of fabricating a photomask 有权

    公开(公告)号：US11415876B2

    公开(公告)日：2022-08-16

    申请号：US17030941

    申请日：2020-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kangmin Jung ,  Sangwook Park ,  Youngdeok Kwon ,  Myungsoo Noh

    IPC: G03F1/36 ,  G03F1/22

    Abstract: The present disclosure relates to a fabrication method of a photomask. The method of fabricating a photomask provides for a layout of patterns to be designed. The layout of patterns may be formed on a wafer on which chips are formed. The layout of patterns are corrected to provide a layout of a photoresist pattern serving as an etching mask for forming the patterns on the wafer while generating a flare map of the patterns. An optical proximity correction (OPC) may be performed at a chip level on the corrected layout of patterns to perform a secondary correction of the layout of patterns. A second OPC may be performed at a level of a shot which includes a plurality of ones of the chips by reflecting the flare map on the second corrected layout of patterns to a third corrected layout of patterns.

    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT
    20.
    发明申请
    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT 有权

    公开(公告)号：US20220406361A1

    公开(公告)日：2022-12-22

    申请号：US17828200

    申请日：2022-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inseok Baek ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Seokjae Lee

    IPC: G11C11/408

    Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

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