公开(公告)号：US20190157133A1

公开(公告)日：2019-05-23

申请号：US16238172

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/108 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US20230354588A1

公开(公告)日：2023-11-02

申请号：US18117604

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Junhyeok AHN ,  Keunnam KIM ,  Chan-Sic YOON ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/02

Abstract: A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

公开(公告)号：US20230298999A1

公开(公告)日：2023-09-21

申请号：US18047704

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Myeong-Dong LEE

IPC: H01L23/528 ,  H01L21/762 ,  H10B12/00 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76224 ,  H01L27/10885 ,  H01L27/10888 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor memory device may include a device isolation pattern in a substrate and defining a first active section of the substrate and a second active section of the substrate, a first bit line crossing the center of the first active section, a second bit line crossing a center of the second active section, a bit-line contact between the first bit line and a center of the first active section, and a storage node pad on an end of the second active section. The first and second active sections may be spaced apart from each other. The center of the first active section may be adjacent to the end of the second active section. A level of a bottom surface of the first bit line may be lower than a level of a bottom surface of the second bit line.

公开(公告)号：US20210125980A1

公开(公告)日：2021-04-29

申请号：US17132699

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20210020495A1

公开(公告)日：2021-01-21

申请号：US17039431

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US20200219732A1

公开(公告)日：2020-07-09

申请号：US16509792

申请日：2019-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  Min-Su CHOI ,  Jun-Hyeok AHN ,  Sung-Hee HAN ,  Ce-Ra HONG

IPC: H01L21/3213 ,  H01L27/108

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

公开(公告)号：US20190326278A1

公开(公告)日：2019-10-24

申请号：US16288590

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.