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    Flip-flop and semiconductor system including the same
    12.
    发明授权
    Flip-flop and semiconductor system including the same 有权

    公开(公告)号：US10651828B2

    公开(公告)日：2020-05-12

    申请号：US15623412

    申请日：2017-06-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Chul Hwang ,  Ah-Reum Kim ,  Min-Su Kim

    IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/356 ,  H03K19/21

    Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

    Semiconductor circuit and method of operating the circuit
    13.
    发明授权
    Semiconductor circuit and method of operating the circuit 有权

    公开(公告)号：US10587246B2

    公开(公告)日：2020-03-10

    申请号：US16212193

    申请日：2018-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min-Su Kim

    IPC: H03K3/356 ,  H03K3/012 ,  G01R31/3185

    Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

    Unbalanced multiplexer and scan flip-flops applying the same
    14.
    发明授权
    Unbalanced multiplexer and scan flip-flops applying the same 有权

    公开(公告)号：US10436836B2

    公开(公告)日：2019-10-08

    申请号：US15332305

    申请日：2016-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min-Su Kim

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/00 ,  G01R31/3185

    Abstract: An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

    Multi-bit flip-flops
    15.
    发明授权
    Multi-bit flip-flops 有权

    公开(公告)号：US10353000B2

    公开(公告)日：2019-07-16

    申请号：US15479310

    申请日：2017-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doo-Seok Yoon ,  Min-Su Kim ,  Chung-Hee Kim ,  Dae-Seong Lee ,  Hyun Lee ,  Matthew Berzins ,  James Lim

    IPC: G01R31/3177 ,  H03K3/037 ,  G01R31/317

    Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

    Integrated circuit and electronic apparatus including integrated circuit
    16.
    发明授权
    Integrated circuit and electronic apparatus including integrated circuit 有权

    公开(公告)号：US10184984B2

    公开(公告)日：2019-01-22

    申请号：US15140720

    申请日：2016-04-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Chul Hwang ,  Dae-Seong Lee ,  Min-Su Kim

    IPC: G01R31/28 ,  G01R31/3185

    Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.

    METHOD OF OPERATING MEMORY DEVICE AND METHOD OF OPERATING MEMORY SYSTEM
    17.
    发明申请
    METHOD OF OPERATING MEMORY DEVICE AND METHOD OF OPERATING MEMORY SYSTEM 审中-公开

    公开(公告)号：US20180151218A1

    公开(公告)日：2018-05-31

    申请号：US15691828

    申请日：2017-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANG-HO YUN ,  Min-Su Kim ,  Sung-Joon Kim ,  So-Ra Park ,  Hyun-Jung Yoo

    IPC: G11C11/406 ,  G06F3/06

    CPC classification number: G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40618

    Abstract: A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.

    Integrated circuit including complex logic cell
    20.
    发明授权
    Integrated circuit including complex logic cell 有权

    公开(公告)号：US10586809B2

    公开(公告)日：2020-03-10

    申请号：US16211496

    申请日：2018-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju-Hyun Kang ,  Hyun Lee ,  Min-Su Kim ,  Ji-Kyum Kim ,  Jong-Woo Kim

    IPC: H01L27/118 ,  G06F17/50

    Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

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