公开(公告)号：US08742801B2

公开(公告)日：2014-06-03

申请号：US13717931

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Soo Ha ,  Ho-Seok Seol ,  Woo-Jin Lee

IPC: H03K3/00

CPC classification number: H03K19/018514

Abstract: A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved.

Abstract translation: 提供了缓冲电路，其对于占空比失真不敏感，而与操作环境的变化无关。 缓冲电路包括电流模式逻辑缓冲器和差分到单端转换器。 差分到单端转换器接收第一和第二差分输出信号以产生单端输出信号，并且被配置为使得差分到单端转换器的内部控制节点以负反馈方式被控制 保持单端输出信号的恒定占空比，而不管操作环境的变化。 根据一些实施例，减少或最小化由于诸如处理，电压，温度等的操作环境的改变引起的单端输出信号的占空比失真，从而提高缓冲电路的性能和操作可靠性 改进了

公开(公告)号：US12020767B2

公开(公告)日：2024-06-25

申请号：US17539761

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C7/222

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US11749338B2

公开(公告)日：2023-09-05

申请号：US17816138

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US11626181B2

公开(公告)日：2023-04-11

申请号：US17245075

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

IPC: G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

公开(公告)号：US10283186B2

公开(公告)日：2019-05-07

申请号：US15787101

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Hwan Jeon ,  Kyung-Soo Ha ,  Jin-Seok Heo ,  In-Dal Song ,  Jung-Hwan Choi

IPC: G11C11/24 ,  G11C11/402 ,  G11C7/22 ,  G11C11/22 ,  G11C7/10 ,  G11C11/4093

Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

公开(公告)号：US09438232B2

公开(公告)日：2016-09-06

申请号：US14568402

申请日：2014-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Soo Ha

IPC: H03K19/00

CPC classification number: H03K19/0005

Abstract: A semiconductor device is provided. The semiconductor device includes a driver circuit, a dummy circuit, and a control unit. The driver circuit is configured to provide a termination resistor at a signal transmission path. The driver circuit includes a plurality of resistors having at least two different types of resistor. The dummy circuit is electrically connected to the driver circuit and is configured to compensate for a mismatch between the at least two different types of resistors. The control unit is configured to control the dummy circuit, based on a result obtained by detecting the mismatch.

Abstract translation: 提供半导体器件。 半导体器件包括驱动电路，虚拟电路和控制单元。 驱动器电路被配置为在信号传输路径处提供终端电阻器。 驱动器电路包括具有至少两种不同类型的电阻器的多个电阻器。 虚拟电路电连接到驱动器电路并且被配置为补偿至少两种不同类型的电阻器之间的失配。 控制单元被配置为基于通过检测失配而获得的结果来控制虚拟电路。

公开(公告)号：US20150171863A1

公开(公告)日：2015-06-18

申请号：US14568402

申请日：2014-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Soo Ha

IPC: H03K19/00

CPC classification number: H03K19/0005

Abstract: A semiconductor device is provided. The semiconductor device includes a driver circuit, a dummy circuit, and a control unit. The driver circuit is configured to provide a termination resistor at a signal transmission path. The driver circuit includes a plurality of resistors having at least two different types of resistor. The dummy circuit is electrically connected to the driver circuit and is configured to compensate for a mismatch between the at least two different types of resistors. The control unit is configured to control the dummy circuit, based on a result obtained by detecting the mismatch.

Abstract translation: 提供一种半导体器件。 半导体器件包括驱动电路，虚拟电路和控制单元。 驱动器电路被配置为在信号传输路径处提供终端电阻器。 驱动器电路包括具有至少两种不同类型的电阻器的多个电阻器。 虚拟电路电连接到驱动器电路，并且被配置为补偿至少两种不同类型的电阻器之间的失配。 控制单元被配置为基于通过检测失配而获得的结果来控制虚拟电路。

公开(公告)号：US12106794B2

公开(公告)日：2024-10-01

申请号：US18330527

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US11921579B2

公开(公告)日：2024-03-05

申请号：US17692953

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  Jun Hyung Kim ,  Chang-Yong Lee ,  Sang Uhn Cha ,  Kyung-Soo Ha

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772

Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

公开(公告)号：US11508420B2

公开(公告)日：2022-11-22

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.