公开(公告)号：US20220173316A1

公开(公告)日：2022-06-02

申请号：US17330950

申请日：2021-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Dongho AHN ,  Changseung LEE

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided is a semiconductor apparatus including a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.

公开(公告)号：US20250113746A1

公开(公告)日：2025-04-03

申请号：US18980759

申请日：2024-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Dongho AHN ,  Changseung LEE

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor apparatus may include a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.

公开(公告)号：US20230042262A1

公开(公告)日：2023-02-09

申请号：US17522197

申请日：2021-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo CHOI ,  Bonwon KOO ,  Yongyoung PARK ,  Hajun SUNG ,  Dongho AHN ,  Kiyeon YANG ,  Wooyoung YANG ,  Changseung LEE

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: Provided are a switching device and a memory device including the switching device. The switching device includes first and second electrodes, and a switching material layer provided between the first and second electrodes and including a chalcogenide. The switching material layer includes a core portion and a shell portion covering a side surface of the core portion. The switching layer includes a material having an electrical resistance greater than an electrical resistance of the core portion, for example in at least one of the core portion or the shell portion.

公开(公告)号：US20220406842A1

公开(公告)日：2022-12-22

申请号：US17523363

申请日：2021-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hajun SUNG ,  Bonwon KOO ,  Segab KWON ,  Yongyoung PARK ,  Dongho AHN ,  Kiyeon YANG ,  Wooyoung YANG ,  Changseung LEE ,  Minwoo CHOI

IPC: H01L27/24 ,  H01L27/22 ,  C01B19/00

Abstract: Provided are a chalcogenide material, and a device and a memory device each including the same. The chalcogenide material may include: germanium (Ge) as a first component; arsenic (As) as a second component; at least one element selected from selenium (Se) and tellurium (Te) as a third component; and at least one element selected from the elements of Groups 2, 16, and 17 of the periodic table as a fourth component, wherein a content of the first component may be from 5 at % to 30 at %, a content of the second component may be from 20 at % to 40 at %, a content of the third component may be from 25 at % to 75 at %, and a content of the fourth component may be from 0.5 at % to 5 at %.

公开(公告)号：US20220082822A1

公开(公告)日：2022-03-17

申请号：US17519347

申请日：2021-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jeongyub LEE ,  Reehyang KIM ,  Jonghwa SHIN ,  Kiyeon YANG ,  Yongsung KIM ,  Jaekwan KIM ,  Changseung LEE ,  Narae HAN

IPC: G02B27/00 ,  G02B5/08 ,  G02B3/02 ,  G02B1/00

Abstract: Provided in a phase shifting device including a plurality of metal layers and a plurality of first dielectric layers, a metal layer of the plurality of metal layers and a first dielectric layer of the plurality of first dielectric layers being alternately stacked in a first direction, and a second dielectric layer disposed on a side surface of the stacked structure in a second direction, wherein the first dielectric layer includes a first material having a first dielectric constant and the second dielectric layer includes a second material having a second dielectric constant, and wherein the second dielectric constant is greater than the first dielectric constant.

公开(公告)号：US20150371855A1

公开(公告)日：2015-12-24

申请号：US14721395

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Namjeong KIM ,  Haesung KIM

IPC: H01L21/04 ,  H01L21/67 ,  H01L29/16 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/042 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/6708 ,  H01L21/67115 ,  H01L29/1606 ,  H01L29/66015

Abstract: According to example embodiments, an apparatus for etching a two-dimensional material layer includes a stage configured to support an etching target including graphene on the stage, a light source configured to emit light having a wavelength that is shorter than a wavelength of visible light, a mask imprinted with a pattern for transferred onto the etching target, a fluid inlet configured to supply a fluid over the etching target, and a fluid outlet configured to absorb a residue and a reaction product after the fluid is supplied over the etching target using the fluid inlet.

Abstract translation: 根据示例性实施例，用于蚀刻二维材料层的设备包括：被配置为在舞台上支撑包括石墨烯的蚀刻靶的台，被配置为发射波长比可见光波长短的光的光源， 用于转印到蚀刻靶上的图案的掩模，被配置为在蚀刻对象上提供流体的流体入口和构造成吸收残留物的流体出口和在使用 流体入口。

公开(公告)号：US20250133970A1

公开(公告)日：2025-04-24

申请号：US18444206

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo CHOI ,  Hajun SUNG ,  Bonwon KOO ,  Kiyeon YANG ,  Changseung LEE

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

Abstract: Provided are a chalcogenide-based memory device capable of implementing multi-level memory and an electronic apparatus including the chalcogenide-based memory device. The memory device includes a first electrode and a second electrode arranged to be spaced apart from each other, and a memory layer provided between the first electrode and the second electrode and including a plurality of memory material layers having different threshold voltages from each other. Each of the plurality of memory material layers includes a chalcogenide-based material, has an ovonic threshold switching (OTS) characteristic, and is configured to have a threshold voltage varying depending on a polarity and intensity of an applied voltage.

公开(公告)号：US20250089270A1

公开(公告)日：2025-03-13

申请号：US18540222

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Haeryong KIM ,  Hajun SUNG ,  Changseung LEE

IPC: H10B63/00 ,  H10B63/10

Abstract: Provided are a memory device, a manufacturing method thereof, and an electronic apparatus including the memory device. The memory device may include a plurality of first conductors arranged apart from each other and perpendicular to a substrate, a second conductor extending perpendicular to the substrate, a chalcogenide layer extending perpendicular to the substrate between the plurality of first conductors and the second conductor, and a plurality of first diffusion barrier layers selectively arranged only on the plurality of first conductors between the plurality of first conductors and the chalcogenide layer. The plurality of first diffusion barrier layers each may include a carbon-based material.

公开(公告)号：US20230380195A1

公开(公告)日：2023-11-23

申请号：US18150123

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Changseung Lee ,  Dongho Ahn

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10 ,  H10B63/24

Abstract: A memory device including a phase-change material includes: a substrate; a first memory cell including a first selection layer and a first phase-change material layer, and a second memory cell including a second selection layer and a second phase-change material layer, wherein the first memory cell and the second memory cell are arranged apart from each other with an insulating layer therebetween in a normal direction of the substrate, wherein the first phase-change material layer and the second phase-change material layer include: a first layer including a thermal confinement material; and a second layer including a phase-change material, respectively, wherein the first layer and the second layer extend in a direction vertical to the substrate, and wherein the first phase-change material layer is physically isolated from the second phase-change material layer by the insulating layer.

公开(公告)号：US20220406844A1

公开(公告)日：2022-12-22

申请号：US17568866

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chungman KIM ,  Bonwon KOO ,  Dongho AHN ,  Kiyeon YANG ,  Zhe WU ,  Chang Seung LEE

IPC: H01L27/24 ,  H01L45/00

Abstract: A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.