公开(公告)号：US10692968B2

公开(公告)日：2020-06-23

申请号：US16697484

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Min Lee ,  Jongryul Jun ,  Eun A Kim ,  Jung-Bum Lim

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/08

Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

公开(公告)号：US10665664B2

公开(公告)日：2020-05-26

申请号：US15897931

申请日：2018-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Lee ,  Hyongsoo Kim ,  Jongryul Jun

IPC: H01L49/02 ,  H01L27/108

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

公开(公告)号：US10439048B2

公开(公告)日：2019-10-08

申请号：US16041025

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Bum Lim ,  Jong-Ryul Jun ,  Eun-A Kim ,  Jong-Min Lee

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/027 ,  H01L49/02 ,  H01L21/033 ,  H01L21/311

Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.

公开(公告)号：US10205809B2

公开(公告)日：2019-02-12

申请号：US15287900

申请日：2016-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Jung Yang ,  Seung-Joo Lee ,  Kwang-Eun Go ,  Kang-Sik Kim ,  Jae-Hoon Woo ,  Jong-Min Lee

IPC: H04M1/02 ,  H05K7/20 ,  H05K9/00 ,  G06F1/16 ,  G06F1/20

Abstract: A method for manufacturing an electronic device, according to the present disclosure, may include: detecting positions of one or more heat sources, which are disposed in a printed circuit board or in a display of the electronic device, or a path of the heat that is diffused from the heat sources; selecting a heat radiating structure to correspond to the positions of the heat sources or the diffusion path; selecting an adiabatic member or a heat radiating member, which is disposed based the selected heat radiating structure to block or radiate the heat transferred from the heat source; and forming the selected heat radiating structure or disposing the selected adiabatic member or heat radiating member on the periphery of the heat source or on the diffusion path. According to various embodiments of the disclosure, the heat radiation improvement can be maximized and/or improved by improving the structure of a heat radiation path of the electronic device and by selecting and disposing heat radiating members in appropriate positions.

公开(公告)号：US09917147B2

公开(公告)日：2018-03-13

申请号：US15159809

申请日：2016-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Lee ,  Hyongsoo Kim ,  Jongryul Jun

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/90 ,  H01L27/10852

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

公开(公告)号：US20250132228A1

公开(公告)日：2025-04-24

申请号：US18675431

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Nara Lee ,  Jong-Min Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor chip and a semiconductor package are provided. The semiconductor chip includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad. Each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

公开(公告)号：US10600805B2

公开(公告)日：2020-03-24

申请号：US16157684

申请日：2018-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Park ,  Jong-Min Lee ,  Seon-Kyung Kim ,  Kee-Jeong Rho ,  Jin-hyun Shin ,  Jong-Hyun Park ,  Jin-Yeon Won

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

公开(公告)号：US20180350957A1

公开(公告)日：2018-12-06

申请号：US16041025

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Bum Lim ,  Jong-Ryul Jun ,  Eun-A Kim ,  Jong-Min Lee

IPC: H01L29/66 ,  H01L49/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L28/00 ,  H01L29/66621

Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.

公开(公告)号：US09379123B2

公开(公告)日：2016-06-28

申请号：US14848423

申请日：2015-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

IPC: H01L21/764 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

公开(公告)号：US20210305190A1

公开(公告)日：2021-09-30

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.