公开(公告)号：US11482288B2

公开(公告)日：2022-10-25

申请号：US17242712

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul Bee Lee ,  Dong Hun Kwak ,  Jong-Chul Park

IPC: G11C16/34 ,  G11C16/08

Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.

公开(公告)号：US11417652B2

公开(公告)日：2022-08-16

申请号：US16360191

申请日：2019-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Keun Lee ,  Jong-Chul Park ,  Sang-Hyun Lee

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a first etch stop layer, a second etch stop layer, and an interlayer insulation layer that are stacked on the gate structure, and a contact plug penetrating the interlayer insulation layer, the second etch stop layer, and the first etch stop layer and contacting a sidewall of the gate structure. The contact plug includes a lower portion having a first width and an upper portion having a second width. A lower surface of the contact plug has a stepped shape.

公开(公告)号：US09735349B2

公开(公告)日：2017-08-15

申请号：US14612323

申请日：2015-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Chul Park ,  Byoung-Jae Bae ,  Shin-Jae Kang ,  Young-Seok Choi

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

公开(公告)号：US09337418B2

公开(公告)日：2016-05-10

申请号：US14208912

申请日：2014-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Chul Park ,  Jae-Hun Seo ,  Byong-Jae Bae ,  Chang-Woo Sun

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228

Abstract: A method of manufacturing magnetoresistive random access memory (MRAM) device includes forming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings.

Abstract translation: 制造磁阻随机存取存储器（MRAM）器件的方法包括以交替和重复的布置在衬底上形成第一和第二图案，在第一和第二图案的顶表面上形成第一封盖层，以及去除第一和第二图案的第一部分 盖层和其下的第二图案的一部分以形成暴露基板的第一开口。 所述方法还包括分别形成填充所述第一开口的下部的源极线，分别形成填充所述第一开口的上部的第二封盖层图案，以及移除所述第一封盖层的第二部分及其下面的第二图案的一部分， 形成露出衬底的第二开口。 然后，将接触塞和垫层一体地形成并依次堆叠在基板上以填充第二开口。