公开(公告)号：US20240347437A1

公开(公告)日：2024-10-17

申请号：US18630122

申请日：2024-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Chun

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A semiconductor package includes a redistribution substrate including a plurality of redistribution layers in an insulating layer and including an upper redistribution and a lower redistribution layer, a first pad structure; a second pad structure on the redistribution substrate and connected to the upper redistribution layer; a through-via extending to electrically connect the second pad structure and the plurality of redistribution layers; and a semiconductor chip, wherein the upper redistribution layer includes an upper pattern portion, a first upper pad portion connected to the first pad structure, and a second pad portion having an upper hole through which the through-via extends, the lower redistribution layer includes a lower pattern portion and a lower pad portion on at least one end of the lower pattern portion and having a lower hole through which the through-via extends, and the second pad structure includes a through-hole through which the through-via extends.

公开(公告)号：US11538783B2

公开(公告)日：2022-12-27

申请号：US17088350

申请日：2020-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US11476176B2

公开(公告)日：2022-10-18

申请号：US17035145

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC: H01L29/40 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/321 ,  H01L23/29 ,  H01L21/3105

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US11444014B2

公开(公告)日：2022-09-13

申请号：US16830361

申请日：2020-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Chun ,  Jin Ho An ,  Teahwa Jeong ,  Jeonggi Jin ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.