公开(公告)号：US10325898B2

公开(公告)日：2019-06-18

申请号：US15635615

申请日：2017-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sharma Deepak ,  Rajeev Ranjan ,  Kuchanuri Subhash ,  Chulhong Park ,  Jaeseok Yang ,  Kwanyoung Chun

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

公开(公告)号：US10930648B2

公开(公告)日：2021-02-23

申请号：US16422199

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/11 ,  H01L23/52 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  H01L27/118 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11504 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L29/417

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US09871122B2

公开(公告)日：2018-01-16

申请号：US15244265

申请日：2016-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook Oh ,  Hyunjae Lee ,  Jaeseok Yang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/32 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L29/6681 ,  H01L21/76816 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/3223

Abstract: A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively.

公开(公告)号：US09779198B2

公开(公告)日：2017-10-03

申请号：US14832307

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daekwon Kang ,  Donggyun Kim ,  Jaeseok Yang ,  Jiyoung Jung ,  Chunghee Kim ,  Ha-Young Kim ,  Sungkeun Park ,  Younggook Park ,  Myungsoo Jang ,  Jintae Kim

IPC: G06F17/50 ,  G03F1/70

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081

Abstract: A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.