公开(公告)号：US10535643B2

公开(公告)日：2020-01-14

申请号：US15973927

申请日：2018-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Tae Lee ,  Han Kim ,  Hyung Joon Kim

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/552 ,  H01L23/427 ,  H01L25/10 ,  H01L23/13 ,  H01L25/065

Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).

公开(公告)号：US10453707B2

公开(公告)日：2019-10-22

申请号：US15791795

申请日：2017-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Seok Cho ,  Hyung Joon Kim ,  Jung Ho Kim ,  Joong Yun Ra ,  Bi O Kim ,  Jae Young Ahn ,  Ki Yong Oh ,  Sung Hae Lee

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/8239 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/108 ,  H01L27/11582

Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.

公开(公告)号：US11723203B2

公开(公告)日：2023-08-08

申请号：US17540688

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US10923464B2

公开(公告)日：2021-02-16

申请号：US16725449

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Tae Lee ,  Han Kim ,  Hyung Joon Kim

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/552 ,  H01L23/427 ,  H01L23/13 ,  H01L23/10 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10

Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first 10 semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated 15 circuit (PMIC).

公开(公告)号：US10672727B2

公开(公告)日：2020-06-02

申请号：US16108202

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Jung Ho Shim ,  Jun Young Won ,  Han Kim

IPC: H01L23/64 ,  H01L23/552 ,  H01L23/12 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, having first and second through-holes, spaced apart from each other, and having a wiring structure that connects the first and second surfaces to each other; a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure; a semiconductor chip disposed in the first through-hole and having connection pads connected to the redistribution layers; a second passive component disposed in the second through-hole and connected to the redistribution layers; a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component; and a second encapsulant encapsulating the support member, the first encapsulant, and the semiconductor chip.

公开(公告)号：US20200020713A1

公开(公告)日：2020-01-16

申请号：US16203790

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung CHOI ,  Hyung Joon Kim ,  Bio Kim ,  Yujin Kim ,  Junggeun Jee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/532

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

公开(公告)号：US10483197B2

公开(公告)日：2019-11-19

申请号：US15962867

申请日：2018-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Jung Jo ,  Hyung Joon Kim ,  Han Kim ,  Bo Min Jeong

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.

公开(公告)号：US20230035916A1

公开(公告)日：2023-02-02

申请号：US17653390

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tea Won Kim ,  Hyung Joon Kim ,  Yong-Suk Tak ,  Yu Rim Kim ,  Kong Soo Lee

IPC: H01L29/786

Abstract: A semiconductor device includes a conductive line that extends in a first direction on a substrate, a first oxide semiconductor layer, including a first crystalline oxide semiconductor material containing a first metal element, on the conductive line, a second oxide semiconductor layer, which is in physical contact with the first oxide semiconductor layer and is connected to the conductive line, on the conductive line, a gate electrode that extends in a second direction, which crosses the first direction, on a side of the second oxide semiconductor layer, and a capacitor structure connected to the second oxide semiconductor layer on the second oxide semiconductor layer and the gate electrode, wherein the second oxide semiconductor layer includes a second crystalline oxide semiconductor material containing the first metal element and second and third metal elements, which are different from the first metal element.

公开(公告)号：US20200350315A1

公开(公告)日：2020-11-05

申请号：US16693889

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Hyung Joon Kim ,  Hyun Jung Lee

IPC: H01L27/108

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

公开(公告)号：US20200013727A1

公开(公告)日：2020-01-09

申请号：US16261609

申请日：2019-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Sang Jong Lee ,  Yoon Seok Seo

IPC: H01L23/552 ,  H01L23/13 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/48

Abstract: A semiconductor package includes: a frame having first and second through-holes spaced apart from each other; passive components disposed in the first through-hole; a semiconductor chip disposed in the second through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; a first encapsulant covering at least portions of the passive components and filling at least portions of the first through-hole; a second encapsulant covering at least portions of the semiconductor chip and filling at least portions of the second through-hole; and a connection structure disposed on the frame, the passive components, and the active surface of the semiconductor chip and including wiring layers electrically connected to the passive components and the connection pads of the semiconductor chip. The second encapsulant has a higher electromagnetic wave absorption rate than that of the first encapsulant.