Case for electronic device
    11.
    外观设计

    公开(公告)号:USD986234S1

    公开(公告)日:2023-05-16

    申请号:US29771888

    申请日:2021-02-25

    Abstract: FIG. 1 is a front perspective view of a case for electronic device, showing our new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is a rear perspective view thereof.
    The broken lines in the drawings figures form no part of the claimed design and depict portions of the case for electronic device that form no part of the claimed design.

    Semiconductor package
    12.
    发明授权

    公开(公告)号:US11410958B2

    公开(公告)日:2022-08-09

    申请号:US17201538

    申请日:2021-03-15

    Abstract: A semiconductor package includes a first connection structure having first and second surfaces and including a first redistribution layer, a first semiconductor chip disposed on the first surface and having a first connection pad electrically connected to the first redistribution layer, a second semiconductor chip disposed around the first semiconductor chip on the first surface and having a second connection pad electrically connected to the first redistribution layer, an interconnection bridge disposed on the second surface to be spaced apart from the second surface and connected to the first redistribution layer through a connection member to electrically connect the first and second connection pads to each other, and a second connection structure disposed on the second surface to embed the interconnection bridge and including a second redistribution layer electrically connected to the first redistribution layer.

    Fan-out semiconductor package
    13.
    发明授权

    公开(公告)号:US10714440B2

    公开(公告)日:2020-07-14

    申请号:US16042644

    申请日:2018-07-23

    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

    SEMICONDUCTOR PACKAGE
    14.
    发明申请

    公开(公告)号:US20200211938A1

    公开(公告)日:2020-07-02

    申请号:US16593300

    申请日:2019-10-04

    Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, a heat-dissipating member, including graphite, which is disposed on the inactive surface of the semiconductor chip; an encapsulant sealing at least a portion of each of the semiconductor chip and the heat-dissipating member, and a connection structure, which includes a redistribution layer electrically connected to the connection pad, disposed on the active surface of the semiconductor chip, and at least a side surface of the heat-dissipating member is coplanar with a side surface of the semiconductor chip.

    Semiconductor package
    16.
    发明授权

    公开(公告)号:US10573589B2

    公开(公告)日:2020-02-25

    申请号:US16105289

    申请日:2018-08-20

    Inventor: Eun Jin Kim Han Kim

    Abstract: A semiconductor package includes a connection member having a first surface and a second surface disposed to oppose each other and including an insulating member having a plurality of insulating layers and a plurality of redistribution layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one of the plurality of redistribution layers includes a dummy electrode pattern in which a plurality of holes are arranged, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude externally from different positions.

    Fan-out semiconductor package
    17.
    发明授权

    公开(公告)号:US10403588B2

    公开(公告)日:2019-09-03

    申请号:US15402383

    申请日:2017-01-10

    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

    Case for electronic device
    20.
    外观设计

    公开(公告)号:USD1043647S1

    公开(公告)日:2024-09-24

    申请号:US29884353

    申请日:2023-02-10

    Designer: Han Kim

    Abstract: FIG. 1 is a front perspective view of a case for electronic device showing my new design;
    FIG. 2 is a front elevation view thereof;
    FIG. 3 is a rear elevation view thereof;
    FIG. 4 is a left side elevation view thereof;
    FIG. 5 is a right side elevation view thereof;
    FIG. 6 is a top plan view thereof;
    FIG. 7 is a bottom plan view thereof; and,
    FIG. 8 is a rear perspective view thereof.
    The broken lines in the figures illustrate portions of the case for electronic device that form no part of the claimed design.

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