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公开(公告)号：US20190273639A1
公开(公告)日：2019-09-05
申请号：US16058896
申请日：2018-08-08
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohammad Hekmat
Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
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公开(公告)号：US09722820B1
公开(公告)日：2017-08-01
申请号：US15194417
申请日：2016-06-27
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Mohammad Hekmat , Amir Amirkhany
CPC classification number: H04L25/03057 , H04B1/16 , H04L25/03146
Abstract: A method of calibrating coefficients of a calibrated decision feedback equalizer (DFE) across a process, voltage, and temperature (PVT) range, the calibrated DFE comprising a plurality of DFE taps for reducing distortions of an input signal, and a sampler for sampling the input signal, the method including applying a preset voltage to an input of the calibrated DFE, setting a DFE tap of the plurality of DFE taps to a maximum value, generating a source reference, via a source reference calibrator, to apply to the DFE tap, changing the source reference to a first level that causes an output of the sampler to transition from a first state to a second state, determining the first level as a calibrated source reference, and applying the calibrated source reference to the DFE tap during normal operation of the calibrated DFE.
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公开(公告)号：US09712177B1
公开(公告)日：2017-07-18
申请号：US14991898
申请日：2016-01-08
Applicant: Samsung Display Co., Ltd.
Inventor： Mohammad Hekmat , Jalil Kamali
CPC classification number: H03L7/1974 , H03K5/131 , H03K2005/00058 , H03L7/087 , H03L7/089 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/16 , H03L7/18
Abstract: A phase-locked loop. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.
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公开(公告)号：US20170178562A1
公开(公告)日：2017-06-22
申请号：US14974535
申请日：2015-12-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Mohammad Hekmat , Amir Amirkhany
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G5/003 , G09G2300/0408 , G09G2310/0221 , G09G2310/0291 , G09G2310/0297 , G09G2370/04 , G09G2370/045
Abstract: A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.
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公开(公告)号：US09531570B2
公开(公告)日：2016-12-27
申请号：US14697550
申请日：2015-04-27
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Mohammad Hekmat , Amir Amirkhany
CPC classification number: H04L25/03057 , H04L2025/03503
Abstract: A system for reduced-rate predictive DFE. In one embodiment a plurality of sampler-multiplexer blocks, each including two samplers and a multiplexer-latch, controlled by a multi-phase clock, sample the received analog signal one at a time, and the output of each multiplexer-latch, which may represent the value of the last received bit, is used to control the select input of another multiplexer-latch, so that the other multiplexer-latch selects the appropriate one of two samplers, each applying a different correction to the received analog signal before sampling. Each multiplexer-latch is a clocked element that tracks the data input when the signal at its clock input has a first logic level and retains its output state when its clock input has another (i.e., a second) logic level.
Abstract translation: 一种降低速率预测DFE的系统。 在一个实施例中，多个采样器 - 多路复用器块，每个包括由多相时钟控制的两个采样器和多路复用器锁存器，一次对接收到的模拟信号进行采样，并且每个多路复用器锁存器的输出可以 表示最后接收的位的值，用于控制另一个多路复用器锁存器的选择输入，使得另一个多路复用器锁存器选择两个采样器中适当的一个采样器，每个采样器在采样之前对接收到的模拟信号施加不同的校正。 每个多路复用器锁存器是当其时钟输入处的信号具有第一逻辑电平时跟踪数据输入的时钟元件，并且当其时钟输入具有另一（即第二）逻辑电平时保持其输出状态。
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Patent Agency Ranking
16.发明申请公开(公告)号：US20150097603A1
公开(公告)日：2015-04-09
申请号：US14290894
申请日：2014-05-29
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Amir Amirkhany , Mohammad Hekmat
IPC: H03K3/017
CPC classification number: H03K3/017 , H03K5/1565
Abstract: An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.
Abstract translation: 电子设备包括被配置为发送第一时钟信号的时钟和用于电子设备的操作的第二时钟信号; 负载周期校正器，耦合到时钟以校正第一和第二时钟信号的占空比，占空比校正器被配置为：响应于第一时钟信号分配和存储第一占空比校正码; 分配并存储响应于第二时钟信号的第二占空比校正码; 基于第一和第二占空比校正码计算偏移码; 并且将偏移代码与占空比校正操作的结果否定。
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公开(公告)号：US20140314172A1
公开(公告)日：2014-10-23
申请号：US14162648
申请日：2014-01-23
Applicant: Samsung Display Co., Ltd.
Inventor： Mohammad Hekmat
CPC classification number: H04L27/06 , H03M1/002 , H03M1/361 , H03M5/20 , H04L25/03878 , H04L25/066 , H04L25/4917
Abstract: A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption.
Abstract translation: 一种用于检测多级信令接收机中的信号电平的系统和方法。 在一个实施例中，每个包括差分对（例如差分对的场效应晶体管（FET））的多个比较器以堆叠配置组装，使得在一些状态下，电流流过多个差分对的FET 系列，导致功耗降低。
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公开(公告)号：US10699669B2
公开(公告)日：2020-06-30
申请号：US16057037
申请日：2018-08-07
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Mohammad Hekmat
Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.
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公开(公告)号：US10140912B2
公开(公告)日：2018-11-27
申请号：US14974535
申请日：2015-12-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Mohammad Hekmat , Amir Amirkhany
IPC: G09G3/20
Abstract: A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.
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公开(公告)号：US20170201261A1
公开(公告)日：2017-07-13
申请号：US14991898
申请日：2016-01-08
Applicant: Samsung Display Co., Ltd.
Inventor： Mohammad Hekmat , Jalil Kamali
CPC classification number: H03L7/1974 , H03K5/131 , H03K2005/00058 , H03L7/087 , H03L7/089 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/16 , H03L7/18
Abstract: A phase-locked loop. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.
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