Display device and method for fabricating the same

    公开(公告)号:US12069918B2

    公开(公告)日:2024-08-20

    申请号:US18230281

    申请日:2023-08-04

    CPC classification number: H10K59/131 H10K59/122 H10K59/1201

    Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

    Display device and method of fabricating the same

    公开(公告)号:US12125836B2

    公开(公告)日:2024-10-22

    申请号:US18395966

    申请日:2023-12-26

    Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.

    Display device
    18.
    发明授权

    公开(公告)号:US12107114B2

    公开(公告)日:2024-10-01

    申请号:US17471679

    申请日:2021-09-10

    CPC classification number: H01L27/156 H01L33/24 H01L33/38 H01L33/44 H01L33/60

    Abstract: A display device includes first banks on a substrate and spaced apart from each other, a first electrode and a second electrode on the first banks and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, and light emitting elements on the first insulating layer and each having ends on the first electrode and the second electrode. Each of the first banks includes a first pattern portion including concave portions and convex portions. The first pattern portions of the first banks are disposed on side surfaces of the first banks. The side surfaces are spaced apart and face each other. Each of the first electrode and the second electrode includes a second pattern portion on the first pattern portion and having a pattern shape corresponding to the first pattern portion on a surface thereof.

    Display device and method of fabricating the same

    公开(公告)号:US11600682B2

    公开(公告)日:2023-03-07

    申请号:US17074323

    申请日:2020-10-19

    Abstract: A display device and a method of driving a display device are provided. A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern, a buffer layer on the first conductive layer, a semiconductor layer including a semiconductor pattern on the buffer layer, a gate insulating layer on the semiconductor pattern, a second conductive layer including a gate electrode on the gate insulating layer, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including a first conductive pattern electrically coupling the lower light blocking pattern to the semiconductor pattern, wherein the first conductive pattern is coupled to the lower light blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor pattern through a second contact hole passing through the planarization layer.

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