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    MEMORY CONTROLLER AND OPERATING METHOD THEREOF
    13.
    发明公开
    MEMORY CONTROLLER AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20230205458A1

    公开(公告)日：2023-06-29

    申请号：US17746304

    申请日：2022-05-17

    Applicant: SK hynix Inc.

    Inventor： Ki Young KIM

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0658 ,  G06F3/0607 ,  G06F3/0679

    Abstract: The embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may include a memory configured to store an activation candidate list including one or more nodes each indicating a logical address range that satisfies a preset activation candidate condition, and a processor configured to determine a target node based on activation parameters of logical address ranges indicated by respective nodes included in the activation candidate list, determine, as activation logical address ranges, one or more logical address ranges from the activation candidate list based on the target node, and transmit information indicating the activation logical address range to a host.

    MEMORY DEVICE FOR PERFORMING CONVOLUTION OPERATION
    14.
    发明申请
    MEMORY DEVICE FOR PERFORMING CONVOLUTION OPERATION 有权

    公开(公告)号：US20230043170A1

    公开(公告)日：2023-02-09

    申请号：US17565915

    申请日：2021-12-30

    Applicant: SK hynix Inc.

    Inventor： Young Jae JIN ,  Ki Young KIM ,  Sang Eun JE

    IPC: G06N3/063 ,  G06F7/544 ,  G06F7/50 ,  G06F7/523 ,  H03M1/12

    Abstract: A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

    APPARATUS AND METHOD FOR TRANSMITTING METADATA GENERATED BY A NON-VOLATILE MEMORY SYSTEM
    15.
    发明申请
    APPARATUS AND METHOD FOR TRANSMITTING METADATA GENERATED BY A NON-VOLATILE MEMORY SYSTEM 有权

    公开(公告)号：US20220197509A1

    公开(公告)日：2022-06-23

    申请号：US17384543

    申请日：2021-07-23

    Applicant: SK hynix Inc.

    Inventor： Ki Young KIM

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A memory system includes a memory device including memory blocks, each memory block including a memory cell capable of storing a multi-bit data item. The memory device includes a write booster region including at least one memory block among the plurality of memory blocks, the at least one memory block including a memory cell storing a single-bit data item. A controller is configured to assign a memory block in the write booster region to a host performance booster (HPB) region when the memory block is closed and transmit to a host an indication that the memory block is assigned to the HPB region.

    SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR CHIP HAVING A REDISTRIBUTION LAYER
    16.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR CHIP HAVING A REDISTRIBUTION LAYER 有权

    公开(公告)号：US20210366853A1

    公开(公告)日：2021-11-25

    申请号：US17002422

    申请日：2020-08-25

    Applicant: SK hynix Inc.

    Inventor： Jong Hyun KIM ,  Seung Hwan KIM ,  Hyun Chul SEO ,  Ki Young KIM

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L23/532

    Abstract: A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is omitted.

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