公开(公告)号：US20200272585A1

公开(公告)日：2020-08-27

申请号：US16600823

申请日：2019-10-14

Applicant: SK hynix Inc.

Inventor： Joo Young KIM ,  Yong Sang PARK ,  Jae Hyeok JANG ,  Young Jae JIN

IPC: G06F13/16

Abstract: There are provided a memory controller and a memory system having the same. The memory controller is included in the memory system for storing data and transmits data between the memory system and a host system. The memory controller includes: a buffer including a plurality of blocks for storing the data, the buffer inputting or outputting the data through a first bus having a first data width or a second bus having a second data width; and a data width controller for mapping the blocks according to the first and second data widths.

公开(公告)号：US20230096854A1

公开(公告)日：2023-03-30

申请号：US17705068

申请日：2022-03-25

Applicant: SK hynix Inc.

Inventor： Young Jae JIN ,  Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  G06N3/04 ,  G06K9/62

Abstract: A data processing system includes a controller and a computation device. The controller receives a request for processing a neural network computation from a host, the request including an input feature map and a weight filter. The computation device includes a storage unit allocated to each of integration groups, and performs a convolution operation on the input feature map and the weight filter, sequentially outputs pooling elements as a result of the convolution operation, and performs a pooling operation on the pooling elements. The pooling elements corresponds to each integration group. The computation device performs the pooling operation by integrating a pooling value read from the storage unit and each of the pooling elements into a single value and updating the pooling value stored in the storage unit with a result of the integrating. The integrating and the updating are repeated until all of the pooling elements are integrated.

公开(公告)号：US20230043170A1

公开(公告)日：2023-02-09

申请号：US17565915

申请日：2021-12-30

Applicant: SK hynix Inc.

Inventor： Young Jae JIN ,  Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  G06F7/544 ,  G06F7/50 ,  G06F7/523 ,  H03M1/12

Abstract: A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

公开(公告)号：US20210319291A1

公开(公告)日：2021-10-14

申请号：US17151561

申请日：2021-01-18

Applicant: SK hynix Inc.

Inventor： Yong Sang PARK ,  Joo Young KIM ,  Young Jae JIN

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: A neural network computation apparatus includes a first processing block including a plurality of processing units that each perform a matrix multiplication operation on input data and weights, and a second processing block including a plurality of element-wise operation processing groups. The element-wise operation processing group selectively perform a first neural network computation operation and a second neural network computation operation. The first neural network computation operation comprises the matrix multiplication operation on the input data and the weights and an activation operation on a result value of the matrix multiplication operation, and the second neural network computation operation comprises an activation operation on the result value of the matrix multiplication operation, which is transferred from the first processing block, and an element-wise operation.

公开(公告)号：US20210181951A1

公开(公告)日：2021-06-17

申请号：US16911086

申请日：2020-06-24

Applicant: SK hynix Inc.

Inventor： Young Jae JIN

IPC: G06F3/06 ,  G06N3/063 ,  G06N3/04

Abstract: A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.

公开(公告)号：US20200257959A1

公开(公告)日：2020-08-13

申请号：US16597373

申请日：2019-10-09

Applicant: SK hynix Inc.

Inventor： Young Jae JIN

IPC: G06N3/04 ,  G06F12/06

Abstract: A memory device includes a memory configured to store data and a score computation block configured to compute scores for the data stored in the memory and output at least one data having a score equal to or greater than a threshold value among computed scores. The memory device also includes an address generation block configured to generate and output final position information to be accessed, based on the at least one data outputted from the score computation block. The memory device further includes a data read/write block configured to perform a read operation and a write operation for data which matches the final position information in the memory.

公开(公告)号：US20230061729A1

公开(公告)日：2023-03-02

申请号：US17721727

申请日：2022-04-15

Applicant: SK hynix Inc.

Inventor： Young Jae JIN

IPC: G06N3/063 ,  G06N3/04 ,  G06F9/54 ,  G06F9/48

Abstract: A data processing system includes a controller configured to receive a neural network operation processing request from a host device; and an in-memory computing device including a plurality of processing elements. The in-memory computing device is configured to receive an input feature map and a weight filter from the controller, and perform a neural network operation in the plurality of processing elements based on the weight filter and a plurality of division maps generated from the input feature map, wherein the in-memory computing device performs the neural network operation by not moving a reused element, which is operated at least twice among elements constituting the division maps during the neural network operation, between the processing elements.

公开(公告)号：US20200250060A1

公开(公告)日：2020-08-06

申请号：US16659129

申请日：2019-10-21

Applicant: SK hynix Inc.

Inventor： Young Jae JIN ,  Joo Young KIM ,  Yong Sang PARK

IPC: G06F11/30 ,  G06F13/16 ,  G06F9/48 ,  G11C11/409 ,  G11C11/408

Abstract: A memory controller includes a temperature monitor configured to update temperature states of a memory device divided into groups as temperature scores and a scheduler configured to update a command score using the temperature scores and change a priority of the command score to match with a current operation mode.

公开(公告)号：US20190324690A1

公开(公告)日：2019-10-24

申请号：US16200985

申请日：2018-11-27

Applicant: SK hynix Inc.

Inventor： Young Jae JIN

IPC: G06F3/06

Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a temperature monitor device configured to count values that vary according to operation statuses of memory devices; a status check device configured to output status information of the memory devices based on the count values; and a scheduler configured to store the status information according to arrangements of the memory devices, and output the status information in response to a request received from a host.