公开(公告)号：US20230043170A1

公开(公告)日：2023-02-09

申请号：US17565915

申请日：2021-12-30

Applicant: SK hynix Inc.

Inventor： Young Jae JIN ,  Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  G06F7/544 ,  G06F7/50 ,  G06F7/523 ,  H03M1/12

Abstract: A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

公开(公告)号：US20230113627A1

公开(公告)日：2023-04-13

申请号：US17703873

申请日：2022-03-24

Applicant: SK hynix Inc.

Inventor： Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  H03M1/36 ,  G11C13/00 ,  G06F7/544

Abstract: Provided herein may be an electronic device. The electronic device may include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines a maximum value allowed to the analog signal voltage based on the reference voltage.

公开(公告)号：US20230096854A1

公开(公告)日：2023-03-30

申请号：US17705068

申请日：2022-03-25

Applicant: SK hynix Inc.

Inventor： Young Jae JIN ,  Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  G06N3/04 ,  G06K9/62

Abstract: A data processing system includes a controller and a computation device. The controller receives a request for processing a neural network computation from a host, the request including an input feature map and a weight filter. The computation device includes a storage unit allocated to each of integration groups, and performs a convolution operation on the input feature map and the weight filter, sequentially outputs pooling elements as a result of the convolution operation, and performs a pooling operation on the pooling elements. The pooling elements corresponds to each integration group. The computation device performs the pooling operation by integrating a pooling value read from the storage unit and each of the pooling elements into a single value and updating the pooling value stored in the storage unit with a result of the integrating. The integrating and the updating are repeated until all of the pooling elements are integrated.

公开(公告)号：US20230040775A1

公开(公告)日：2023-02-09

申请号：US17534212

申请日：2021-11-23

Applicant: SK hynix Inc.

Inventor： Ji Hoon NAM ,  Sang Eun JE

IPC: G06F3/06 ,  G06F7/50 ,  G06F7/523

Abstract: A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

公开(公告)号：US20220385295A1

公开(公告)日：2022-12-01

申请号：US17521603

申请日：2021-11-08

Applicant: SK hynix Inc.

Inventor： Sang Eun JE ,  Ki Young KIM

IPC: H03M1/00 ,  G06N3/063 ,  G11C13/00

Abstract: An electronic device includes analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal, an analog input signal generator configured to generate analog input signals provided to each analog-to-digital converter based on input voltages and weight data, an input signal distribution information generator configured to generate input signal distribution information indicating a distribution of the analog input signals for each of the analog-to-digital converters, an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information, and an analog-to-digital converter input range optimizer configured to determine an input range of each first analog-to-digital converter group based on the input signal distribution information, and each analog-to-digital converter is configured to operate according to an input range of a corresponding first analog-to-digital converter groups.