公开(公告)号：US11227815B2

公开(公告)日：2022-01-18

申请号：US16827746

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor die includes first pads, switches that are electrically connected with the first pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the first pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the first pads based on a result of the operations, and a switch controller that controls the switches so that the first pads communicate with the test signal generator during a test operation and that the first pads communicate with the internal circuits after a completion of the test operation.

公开(公告)号：US20230223056A1

公开(公告)日：2023-07-13

申请号：US18125260

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C16/24 ,  H10B80/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  H10B80/00 ,  G11C16/0483

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US11348848B2

公开(公告)日：2022-05-31

申请号：US17006186

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L27/11573 ,  H01L21/66 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell region including first pads and a peripheral circuit region including second pads. The regions comprises switches that are electrically connected with the pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the pads based on a result of the operations, and a switch controller that controls the switches so that the pads communicate with the test signal generator during a test operation and that the pads communicate with the internal circuits after a completion of the test operation. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11289150B2

公开(公告)日：2022-03-29

申请号：US17196183

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Taehyo Kim ,  Daeseok Byeon ,  Seungwon Lee

IPC: G11C11/40 ,  G11C11/4072 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4099

Abstract: A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

公开(公告)号：US11264082B2

公开(公告)日：2022-03-01

申请号：US17024267

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20210125659A1

公开(公告)日：2021-04-29

申请号：US17024267

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.