公开(公告)号：US20220231039A1

公开(公告)日：2022-07-21

申请号：US17685692

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H01L27/11556 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US11257708B2

公开(公告)日：2022-02-22

申请号：US16377516

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US20210020656A1

公开(公告)日：2021-01-21

申请号：US16802736

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US11877451B2

公开(公告)日：2024-01-16

申请号：US17162408

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Kangmin Kim ,  Kyeongjin Park ,  Seungmin Song ,  Joongshik Shin ,  Geunwon Lim

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

公开(公告)号：US11276706B2

公开(公告)日：2022-03-15

申请号：US15930867

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim ,  Yoonhwan Son ,  Junyoung Choi

IPC: H01L27/11582 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11565

Abstract: Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.

公开(公告)号：US11271003B2

公开(公告)日：2022-03-08

申请号：US16856560

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H01L27/11556 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US10910396B2

公开(公告)日：2021-02-02

申请号：US16444716

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Kwang-soo Kim

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.

公开(公告)号：US20210020648A1

公开(公告)日：2021-01-21

申请号：US16856560

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H01L27/11556 ,  H01L29/788 ,  G11C5/02

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US10861876B2

公开(公告)日：2020-12-08

申请号：US16846933

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon Lim ,  Hwan Lee

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/105 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

公开(公告)号：US20250031364A1

公开(公告)日：2025-01-23

申请号：US18906403

申请日：2024-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.