公开(公告)号：US11062784B2

公开(公告)日：2021-07-13

申请号：US16844317

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US09881685B2

公开(公告)日：2018-01-30

申请号：US15461835

申请日：2017-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chi Weon Yoon ,  Donghyuk Chae ,  Jae-Woo Park ,  Sang-Wan Nam

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

公开(公告)号：US09947416B2

公开(公告)日：2018-04-17

申请号：US14811380

申请日：2015-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chi Weon Yoon ,  Donghyuk Chae ,  Jae-Woo Park ,  Sang-Wan Nam

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

公开(公告)号：US09378833B2

公开(公告)日：2016-06-28

申请号：US14788109

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinman Han ,  Donghyuk Chae

IPC: G11C16/14 ,  G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

Abstract: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

公开(公告)号：US09224489B2

公开(公告)日：2015-12-29

申请号：US13920630

申请日：2013-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyuk Chae ,  Jinman Han

IPC: G06F11/00 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

Abstract: Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

Abstract translation: 集成电路存储器件包括非易失性N位存储器单元的阵列，其中N是大于1的整数。 还提供控制电路以可靠地从N位存储器单元读取数据。 电耦合到阵列的该控制电路被配置为确定存储在阵列中的所选N位存储器单元中的至少一位数据的值。 这是通过使用施加到所选择的N位存储器的对应的多个不等的读取电压来解码从所选择的N位存储器单元读取的至少一个硬数据值和多个软数据值（例如，6个数据值）来完成的 在读操作期间。

公开(公告)号：US08964476B2

公开(公告)日：2015-02-24

申请号：US13867716

申请日：2013-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/115 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract translation: 非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。