公开(公告)号：US20220208784A1

公开(公告)日：2022-06-30

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20220157754A1

公开(公告)日：2022-05-19

申请号：US17381782

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong PARK ,  Chanho KIM ,  Pansuk KWAK ,  Daeseok BYEON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L25/00

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US20220093629A1

公开(公告)日：2022-03-24

申请号：US17242696

申请日：2021-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Chanho KIM ,  Kyunghwa YUN ,  Dongseong KIM

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device and an electronic system, the semiconductor device including a semiconductor substrate; a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuits; a semiconductor layer on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor layer, the metal structure including first portions extending in a first direction, second portions connected to the first portions and extending in a second direction crossing the first direction, and a via portion vertically extending from at least one of the first and second portions and being connected to the landing pad; and a stack including insulating layers and electrodes vertically and alternately stacked on the metal structure.

公开(公告)号：US20210366892A1

公开(公告)日：2021-11-25

申请号：US17393934

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho KIM ,  Dongku KANG ,  Daeseok BYEON

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US20210118861A1

公开(公告)日：2021-04-22

申请号：US16940333

申请日：2020-07-27

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Kyunghwa YUN ,  Chanho KIM ,  Dongku KANG

IPC: H01L25/18 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US20210066320A1

公开(公告)日：2021-03-04

申请号：US16944733

申请日：2020-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho KIM ,  Dongku KANG ,  Daeseok BYEON

IPC: H01L27/112 ,  H01L27/24 ,  H01L27/108 ,  H01L27/11585

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US20210066280A1

公开(公告)日：2021-03-04

申请号：US16942854

申请日：2020-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong PARK ,  Chanho KIM ,  Daeseok BYEON

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A memory device includes a memory cell chip, a peripheral circuit chip, and a routing wire. The memory cell chip includes a memory cell array disposed on a first substrate, and a first metal pad on a first uppermost metal layer. The peripheral circuit chip includes circuit devices disposed on a second substrate, and a second metal pad on a second uppermost metal layer of the peripheral circuit chip. The memory cell chip and the peripheral circuit chip are vertically connected to each other by the first metal pad and the second metal pad in a bonding area. The routing wire is electrically connected to the peripheral circuit and is disposed in the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the memory cell chip and the peripheral circuit chip are not electrically connected to each other.

公开(公告)号：US20210043641A1

公开(公告)日：2021-02-11

申请号：US17001035

申请日：2020-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.