公开(公告)号：US20150041884A1

公开(公告)日：2015-02-12

申请号：US14301328

申请日：2014-06-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L29/0611 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1

Abstract translation: 提供了一种功率半导体器件，包括：第一导电类型的第一半导体区域; 形成在第一半导体区域中并且是第二导电类型的第二半导体区域; 形成在第二半导体区域上方并且是第二导电类型的阱区; 以及形成在阱区中并且是第一导电类型的源区，其中第二半导体区包括从器件的下部在器件的高度方向延伸的1至n层，并且在该情况下 第n层的第二半导体区域的最宽宽度为Pn，P1

公开(公告)号：US08742452B2

公开(公告)日：2014-06-03

申请号：US13761127

申请日：2013-02-06

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kwang Soo Kim ,  Bum Seok Suh ,  In Hyuk Song ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397

Abstract: Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region.

Abstract translation: 本发明公开了一种半导体器件及其制造方法。 半导体器件包括半导体衬底，形成在半导体衬底的内部的上部区域中的基极区域，穿过基极区域并具有倒三角形形状的至少一个栅极电极，形成为封闭 半导体衬底的上部和栅电极，形成在栅极电极和栅极绝缘膜的上部的层间绝缘膜，形成在基极区域内和栅电极两侧的发射极区域， 形成在基极区域的上部的发射极金属层和层间绝缘膜，以及形成为包围栅电极的下部并与基极间隔开的缓冲区域。

公开(公告)号：US20140117374A1

公开(公告)日：2014-05-01

申请号：US13758946

申请日：2013-02-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  Chang Su Jang ,  In Hyuk Song ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L29/20 ,  H01L29/00

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/861 ,  H01L29/872

Abstract: Disclosed herein is a semiconductor device including: a base substrate; a first nitride semiconductor layer formed on the base substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a cathode electrode formed on one side of the second nitride semiconductor layer; an anode electrode having one end and the other end, one end being recessed at the other side of the second nitride semiconductor layer up to a predetermined depth, and the other end being spaced apart from the cathode electrode and formed to be extended up to an upper portion of the cathode electrode; and an insulating film formed on the second nitride semiconductor layer between the anode electrode and the cathode electrode so as to cover the cathode electrode.

Abstract translation: 本文公开了一种半导体器件，包括：基底; 形成在所述基底基板上的第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 阴极，形成在所述第二氮化物半导体层的一侧上; 具有一端和另一端的阳极，一端在第二氮化物半导体层的另一侧凹入达预定深度，另一端与阴极间隔开并形成为延伸至 阴极电极的上部; 以及在阳极电极和阴极电极之间形成在第二氮化物半导体层上以覆盖阴极电极的绝缘膜。

公开(公告)号：US20140048845A1

公开(公告)日：2014-02-20

申请号：US13707582

申请日：2012-12-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dong Soo Seo ,  In Hyuk Song ,  Jae Hoon Park

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/7397

Abstract: Disclosed herein are a semiconductor device and a method for manufacturing the same, the semiconductor device including: trench gate electrodes formed in a semiconductor substrate; a gate insulating film covering an upper surface of the semiconductor substrate and lateral surfaces and lower surfaces of the trench gate electrodes; a base region formed between the trench gate electrodes; an emitter region formed between the trench gate electrodes and on the base region; interlayer insulating films formed on the trench gate electrodes and spaced apart from each other; an emitter metal layer formed on the interlayer insulating films and between the interlayer insulating films.

Abstract translation: 这里公开了一种半导体器件及其制造方法，该半导体器件包括形成在半导体衬底中的沟槽栅电极; 覆盖半导体衬底的上表面和沟槽栅电极的侧表面和下表面的栅极绝缘膜; 形成在所述沟槽栅电极之间的基极区域; 形成在所述沟槽栅电极之间和所述基极区上的发射极区域; 在沟槽栅电极上形成并间隔开的层间绝缘膜; 形成在层间绝缘膜上和层间绝缘膜之间的发射极金属层。

公开(公告)号：US20140048844A1

公开(公告)日：2014-02-20

申请号：US13692449

申请日：2012-12-03

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/7397

Abstract: Disclosed herein is a trench gate type power semiconductor device including: a semiconductor substrate; a drift layer formed on the semiconductor substrate; a well layer formed on the drift layer; trenches formed to arrive at the drift layer while penetrating through the well layer in a thickness direction; first insulating films formed from bottom surfaces of the trenches up to a predetermined height; first electrodes formed at a height lower than that of the first insulating films in the trenches; interlayer dielectrics formed up to the same height as that of the first insulating films in the trenches; and a second electrode formed on the well layer, a portion of the first surface corresponding to the trenches being protruded into the trenches to contact the interlayer dielectrics.

Abstract translation: 本文公开了一种沟槽栅型功率半导体器件，包括：半导体衬底; 形成在半导体衬底上的漂移层; 在漂移层上形成的阱层; 形成为在厚度方向穿透阱层时到达漂移层的沟槽; 由沟槽的底面形成的预定高度的第一绝缘膜; 形成在比沟槽中的第一绝缘膜低的高度的第一电极; 形成与沟槽中的第一绝缘膜的高度相同的高度的层间电介质; 以及形成在所述阱层上的第二电极，所述第一表面的与所述沟槽对应的部分突出到所述沟槽中以与所述层间电介质接触。

公开(公告)号：US09318599B2

公开(公告)日：2016-04-19

申请号：US14331603

申请日：2014-07-15

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jae Kyu Sung ,  Jae Hoon Park ,  Kee Ju Um ,  In Hyuk Song

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7397

Abstract: A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on the drift layer so as to contact the trench gate; a first conductive type source region formed on the well region so as to contact the trench gate; and a device protection region formed below a height of a lowermost portion of the source region in a height direction.

Abstract translation: 功率半导体器件可以包括：形成有沟槽栅极的第一导电型漂移层; 形成在所述漂移层上以与所述沟槽栅极接触的第二导电类型阱区; 形成在所述阱区上以便与所述沟槽栅极接触的第一导电型源极区; 以及在高度方向上形成在源极区域的最下部的高度以下的器件保护区域。

公开(公告)号：US09184247B2

公开(公告)日：2015-11-10

申请号：US13795858

申请日：2013-03-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Kee Ju Um ,  Chang Su Jang ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/732 ,  H01L29/739 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/66348 ,  H01L29/7397

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract translation: 这里公开了功率半导体器件。 功率半导体器件包括形成为与第二导电类型阱层的一侧接触的第二导电型第一结端接延伸（JTE）层，形成在其上的第二导电型第二JTE层 线作为第二导电型第一JTE层，并且形成为在基板的长度方向上与第二导电型第一JTE层间隔开，并且形成为与第二导电型第一JTE层接触的多晶硅层 第二导电类型阱层和第二导电型第一JTE层的上部。

公开(公告)号：US09153678B2

公开(公告)日：2015-10-06

申请号：US13871082

申请日：2013-04-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  In Hyuk Song ,  Chang Su Jang ,  Jaehoon Park ,  Dong Soo Seo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract translation: 提供了一种功率半导体器件，包括形成在有源区中的触点，从第一区延伸形成第一终端区并与触点交替形成的沟槽栅，形成在有源区的触点和 沟槽栅极，形成在第一端接区域中的第一导电阱延伸部分和第二端接区域的一部分，以及形成在第二端接区域中并接触阱延伸部分的第一导电场限制环。

公开(公告)号：US20140167150A1

公开(公告)日：2014-06-19

申请号：US13871082

申请日：2013-04-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju UM ,  In Hyuk Song ,  Chang Su Jang ,  Jaehoon Park ,  Dong Soo Seo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract translation: 提供了一种功率半导体器件，包括形成在有源区中的触点，从第一区延伸形成第一终端区并与触点交替形成的沟槽栅，形成在有源区的触点和 沟槽栅极，形成在第一端接区域中的第一导电阱延伸部分和第二端接区域的一部分，以及形成在第二端接区域中并接触阱延伸部分的第一导电场限制环。

公开(公告)号：US20140145291A1

公开(公告)日：2014-05-29

申请号：US13795858

申请日：2013-03-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Kee Ju Um ,  Chang Su Jang ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/06

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/66348 ,  H01L29/7397

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract translation: 这里公开了功率半导体器件。 功率半导体器件包括形成为与第二导电类型阱层的一侧接触的第二导电型第一结端接延伸（JTE）层，形成在其上的第二导电型第二JTE层 线作为第二导电型第一JTE层，并且形成为在基板的长度方向上与第二导电型第一JTE层间隔开，并且形成为与第二导电型第一JTE层接触的多晶硅层 第二导电类型阱层和第二导电型第一JTE层的上部。