公开(公告)号：US20180226135A1

公开(公告)日：2018-08-09

申请号：US15947075

申请日：2018-04-06

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C11/418 ,  G11C29/18 ,  G11C29/02 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412 ,  G11C11/406 ,  G11C8/16 ,  G11C8/10

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20170309327A1

公开(公告)日：2017-10-26

申请号：US15648702

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417 ,  G11C11/413 ,  G11C5/06 ,  G11C5/14 ,  H01L27/11 ,  H01L27/092

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

公开(公告)号：US20170263333A1

公开(公告)日：2017-09-14

申请号：US15606562

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20150279454A1

公开(公告)日：2015-10-01

申请号：US14658163

申请日：2015-03-14

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract translation: 提供的半导体存储装置可以增加写入裕度并抑制芯片面积的增加。 半导体存储装置包括以矩阵形式布置的多个存储单元; 对应于存储器单元的每列布置的多个位线对; 写入驱动器电路，根据写入数据将数据发送到所选列的位线对; 以及将所选列的位线对的低电位侧的位线驱动到负电压电平的写辅助电路。 写辅助电路包括第一信号线; 第一驱动电路，其根据控制信号驱动第一信号布线; 以及第二信号布线，其通过与第一信号布线的线间耦合电容通过第一驱动电路的驱动而耦合到低电位侧的位线并产生负电压。